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UPD17016

更新时间: 2024-11-01 11:47:03
品牌 Logo 应用领域
日电电子 - NEC 微控制器
页数 文件大小 规格书
324页 1246K
描述
4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

UPD17016 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD17016, 17017  
4-BIT SINGLE-CHIP MICROCONTROLLERS WITH  
DIGITAL TUNING SYSTEM HARDWARE  
The µPD17016 and 17017 are 4-bit single-chip CMOS microcontrollers equipped with hardware for digital tuning  
systems.  
The CPU employs the 17K architecture and can directly manipulate the data memory, execute various operations,  
and control the peripheral hardware with a single instruction. All the instructions are one-word 16-bit instructions.  
As the peripheral hardware, a prescaler that can operate at up to 150 MHz, PLL frequency synthesizer, and  
frequency counter for digital tuning systems, as well as many I/O ports, an LCD controller/driver, A/D converter, and  
D/A converter (PWM output) are provided.  
Therefore, a high-performance, state-of-the-art digital tuning system can be organized with a single chip.  
In addition to the µPD17016 and 17017, a one-time PROM model for program evaluation, the µPD17P005, is also  
available.  
FEATURES  
17K architecture: general-purpose register method  
Program memory (ROM)  
A wealth of peripheral hardware  
General-purpose I/O ports, LCD controller/driver, se-  
rial interface, A/D converter, D/A converter (PWM  
output), BEEP output, frequency counter  
Interrupt  
8 KB (3836 × 16 bits) : µPD17016  
16 KB (7932 × 16 bits) : µPD17017  
General-purpose data memory (RAM)  
320 × 4 bits: µPD17016  
External: 1  
432 × 4 bits: µPD17017  
Internal: 1  
Instruction execution time  
Power-ON reset, reset by CE pin, and power failure  
detection circuit  
4.44 µs (with 4.5-MHz crystal resonator)  
Decimal operation  
Power-saving CMOS  
Table reference  
Supply voltage: VDD = 5 V±10%  
Hardware for PLL frequency synthesizer  
Dualmodulusprescaler(150MHzmax.),programmable  
divider, charge pump  
Unless otherwise specified, the µPD17017 is explained as the representative model in this document.  
The inform ation in this docum ent is subject to change w ithout notice.  
Document No. U10664EJ2V0DS00 (2nd edition)  
Date Published September 1996 P  
Printed in Japan  
The mark  
shows major revised points.  
1996  
©

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