Datasheet > UPC8125GR_99

UPC8125GR_99

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
日电电子 - NEC		PC
页数	文件大小	规格书
15页	177K
描述
SILICON MMIC UPCONVERTER WITH AGC + IQ MODULATOR

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数据手册

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UPC8125GR_99 数据手册

SILICON MMIC UPCONVERTER

WITH AGC + IQ MODULATOR

UPC8125GR

INTERNAL BLOCK DIAGRAM

FEATURES

• WIDE SUPPLY VOLTAGE RANGE: 2.7 to 5.5 V

• OUTPUT FREQUENCY RANGE: 1.8 to 2.0 GHz

Vcc (MOD)

Reg.

Vcc (Up-con)

RFout

Filter 1

Filter 2

•

INTERNAL LPF TO REJECT LO & SPURIOUS

LEAKAGE

18 GND

•

PORTS FOR EXTERNAL IF FILTER

AGC FUNCTION: 40 dB RANGE

POWER SAVE FUNCTION

GND

–

Vps

15 VAGC

–

SMALL 20 PIN SSOP PACKAGE

TAPE AND REEL PACKAGING AVAILABLE

GND

Lo2 in

GND

Lo1 in

x 2

LPF LPF

90 deg. Phase

Shifter (÷ 2)

GND 10

DESCRIPTION

was specifically designed for digital mobile communication

applications such as 1900 MHz PCS and PHS handsets.

The UPC8125GR is a Silicon MMIC manufactured with the

NESAT^TMIIIsilicon bipolar process. The IC consists of a 1.8 -

2.0GHzupconverterwithAGCfunctionanda220-270MHzIQ

modulator. The device operates over a wide 2.7 - 5.5 V supply

voltage range and features a power save function. The device

NEC's stringent quality assurance and test procedures ensure

the highest reliability and performance.

ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = VPS = 3.0 V, unless otherwise specified)

PART NUMBER

UPC8125GR

PACKAGE OUTLINE

S20 (SSOP 20)

SYMBOLS

PARAMETERS AND CONDITIONS

Total Circuit Current (no input signal)

UNITS

MIN

TYP

MAX

ICC

ICC(PS)

PRFout 1

PRFout 2

LOL

Total Circuit Current at Sleep Mode

Total Output Power 1

VPS ≤ 0.5 V (Low)

VAGC = 3.0 V

VAGC = 0.5 V

fLO1 + fLO2

µA

dBm

dBc

0.3

-9

-5

-13

Total Output Power 2

-50

-37

-35

-50

Lo Carrier Leak¹

-30

ImR

Image Rejection (Side Band leak)¹

I/Q 3rd Order Intermodulation Distortion¹

AGC Amp. Gain control range

Power Save Rise Time

IM3 I/Q

GCR

VAGC = 2.5 V to 0 V

VPS (OFF) → VPS (ON)

VPS (ON) → VPS (OFF)

fI/Q = 24 kHZ, I → I, Q → Q

I → I, Q → Q

TPS(RISE)

TPS (FALL)

ZI/Q

µS

Power Save Fall Time

µS

Input Impedance I and Q Ports

I/Q Bias Current

kΩ

200

II/Q

µA

ZLO1

Lo1 Input VSWR

fLO1= 220 MHz to 270 MHz

MOD Pattern : PN9

1.2:1

2.5

-68

EVM

Error Vector Magnitude

Adjacent Channel Power

%rms

dBc

4.5

-60

Padj

∆f = 600 KHZ

MOD Pattern : PN9

Notes:

1. VI/Q = 1.5 V (DC) +0.5 Vp-p (AC)

California Eastern Laboratories

12 3 4 5 6 7...15

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