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UPC4094C PDF预览

UPC4094C

更新时间: 2024-10-30 12:16:59
品牌 Logo 应用领域
日电电子 - NEC 运算放大器放大器电路光电二极管输入元件
页数 文件大小 规格书
12页 90K
描述
J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

UPC4094C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:0.300 INCH, PLASTIC, DIP-8Reach Compliance Code:compliant
风险等级:5.88Is Samacsys:N
放大器类型:OPERATIONAL AMPLIFIER最大平均偏置电流 (IIB):0.0002 µA
标称共模抑制比:100 dB最大输入失调电压:3000 µV
JESD-30 代码:R-PDIP-T8JESD-609代码:e0
负供电电压上限:-18 V标称负供电电压 (Vsup):-15 V
功能数量:2端子数量:8
最高工作温度:80 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):230认证状态:Not Qualified
座面最大高度:5.08 mm标称压摆率:25 V/us
供电电压上限:18 V标称供电电压 (Vsup):15 V
表面贴装:NO技术:BIPOLAR
温度等级:COMMERCIAL EXTENDED端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
标称均一增益带宽:6000 kHz宽度:7.62 mm
Base Number Matches:1

UPC4094C 数据手册

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DATA SHEET  
BIPOLAR ANALOG INTEGRATED CIRCUIT  
µPC4094  
J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER  
Dual operational amplifier µPC4094 is a high-speed version of the µPC4092. NEC's unique high-speed PNP  
transistor (fT = 300 MHz) in the output stage realizes a high slew rate of 25 V/µs under voltage-follower conditions  
without an oscillation problem. Zener-zap resistor trimming in the input stage produces excellent offset voltage and  
temperature drift characteristics.  
With AC performance characteristics that are two times better than conventional bi-FET operation amplifiers, the  
µPC4094 is ideal for fast integrators, active filters, and other high-speed circuit applications.  
FEATURES  
Stable operation with 220 pF capacitive load  
Low input offset voltage and offset voltage  
±3 mV (MAX.)  
Low noise : en = 19 nV/ Hz (TYP.)  
Output short circuit protection  
High input impedance ... J-FET Input Stage  
Internal frequency compensation  
High slew rate: 25 V/µs (TYP.)  
±7 µV/°C (TYP.) temperature drift  
Very low input bias and offset currents  
ORDERING INFORMATION  
Part Number  
µPC4094C  
Package  
8-pin plastic DIP (300 mil)  
8-pin plastic SOP (225 mil)  
µPC4094G2  
EQUIVALENT CIRCUIT (1/2 Circuit)  
PIN CONFIGURATION  
(Top View)  
V +  
µ
PC4094C, 4094G2  
Q
Q
9
OUT1  
II1  
1
2
3
4
8
7
6
5
V +  
Q
Q
6
7
1
− +  
I
I
OUT  
Q
1
Q
2
OUT2  
II2  
C1  
2
+ −  
I
N
HIGH SPEED  
PNP  
10  
D
1
IN1  
Q
5
Q
3
Q
4
Q
8
V −  
IN2  
TRIMMED  
V −  
The information in this document is subject to change without notice.  
Document No. G13907EJ1V0DS00 (1st edition)  
Date Published December 1998 N CP(K)  
Printed in Japan  
1998  
©

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