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UPC4092

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日电电子 - NEC 运算放大器输入元件
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12页 88K
描述
J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

UPC4092 数据手册

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DATA SHEET  
BIPOLAR ANALOG INTEGRATED CIRCUIT  
µPC4092  
J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER  
The µPC4092 dual operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable  
AC operating characteristics. NEC's unique high-speed PNP transistor (fT = 300 MHz) in the output stage solves the  
oscillation problem of current sinking with a large capacitive load. Zener-zap resistor trimming in the input stage  
produces excellent offset voltage and temperature drift characteristics.  
FEATURES  
Stable operation with 10000 pF capacitive load  
Low input offset voltage  
Low noise : en = 19 nV/ Hz (TYP.)  
Output short circuit protection  
±3 mV (MAX.)  
High input impedance ... J-FET Input Stage  
Internal frequency compensation  
High slew rate: 15 V/µs (TYP.)  
±7 µV/°C (TYP.) temperature drift  
Very low input bias and offset currents  
ORDERING INFORMATION  
Part Number  
µPC4092C  
Package  
8-pin plastic DIP (300 mil)  
8-pin plastic SOP (225 mil)  
µPC4092G2  
EQUIVALENT CIRCUIT (1/2 Circuit)  
PIN CONFIGURATION  
(Top View)  
V +  
µ
PC4092C, 4092G2  
OUT1  
II1  
1
2
3
4
8
7
6
5
V +  
Q
Q
9
1
− +  
Q
Q
6
7
I
I
OUT2  
II2  
OUT  
Q
1
Q
2
2
+ −  
C1  
I
N
HIGH SPEED  
PNP  
10  
IN1  
D
1
Q
5
Q
3
Q
4
V −  
IN2  
Q
8
TRIMMED  
V −  
The information in this document is subject to change without notice.  
Document No. G13905EJ1V0DS00 (1st edition)  
Date Published December 1998 N CP(K)  
Printed in Japan  
1998  
©

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