3 V DUAL DOWNCONVERTER AND
PLL FREQUENCY SYNTHESIZER
UPB1007K
FEATURES
DESCRIPTION
•
INTEGRATED RF BLOCK:
LNA, RF & IF Downconverter + PLL frequency
synthesizer + on-chip crystal oscillator
NEC'sUPB1007KisaSiliconRFICdesignedforlowcostGPS
receivers. The IC combines an LNA, followed by a double-
conversion RF/IF downconverter block and a PLL frequency
synthesizer on one chip. The chip also includes an on-board
crystal oscillator working up to 16 MHz which can be used as
a CPU reference for fast locking. The device operates on a 3
V supply voltage and is housed in a small 36 pin QFN (Quad
Flat No-lead) package, resulting in low power consumption
and reduced board space. The device is manufactured using
the state of the art UHS0 25 GHz fT silicon bipolar process.
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and performance.
•
•
STATE OF THE ART 25 GHz fT UHS0 BIPOLAR
PROCESS
DOUBLE-CONVERSION: f1stIF = 61.380 MHz
f2ndIF = 4.092 MHz
•
•
•
•
ADJUSTABLE GAIN: 20 dB range MIN
FIXED DIVISION PRESCALER
LOW POWER CONSUMPTION: 25 mA @ 3 V
SMALL 36 PIN QFN PACKAGE
Flat lead style for better performance
APPLICATIONS
•
TAPE AND REEL PACKAGING AVAILABLE
•
•
•
LOW POWER HANDHELD GPS RECEIVER
IN-VEHICLE NAVIGATION SYSTEMS
PC/PDA+GPS INTEGRATION
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, unless otherwise specified)
PART NUMBER
PACKAGE OUTLINE
UPB1007K
QFN-36
SYMBOLS
ICC
PARAMETERS AND CONDITIONS
Total Circuit Current, No Signals
Supply Voltage
UNITS
mA
MIN
TYP
25
MAX
31
VCC
V
2.7
3.0
3.3
LNA (fRFin = 1575.42 MHz, ZL = ZS = 50 Ω)
ZLNAin
ZLNAop
P1dBLNA
PGLNA
NFLNA
RF Input Impedance of LNA
Ω
Ω
28 - j38
85 - jx6
-22
RF Output Impedance of LNA
1 dB Compression, Input matched
Power Gain LNA, Input matched, PRFin = -60 dBm
Noise Figure of LNA, Input matched
dBm
dB
dB
14
15
2.8
3.2
10
Mixer (fRFin = 1575.42 MHz, f1stLOin = 1636.80 MHz, PLO = -10 dBm, f1stIF = 61.38 MHz, ZL = ZS = 50 Ω)
ZMIXin
P1dBMIX
PCGMIX
NFMIX
ALO-IF
ALO-RF
ZMIXout
PLL
RF Input Impedance of Mixer
Ω
31 -j103
-25
1 dB Compression (refer to input), Input matched
Power Conversion Gain
dBm
dB
21
Noise Figure of Mixer (SSB), Input matched
LO Leakage to IF Pins, PLO = -10 dBm
LO Leakage to RF Input Pins, PLO = -10 dBm
RF Output Impedance of Mixer
dB
9.5
dBm
dBm
-40
-48
+152 - j9
ICPOH
ICPOL
PLL Charge Pump High Side Current @ VCPout = VCC/2
PLL Charge Pump Low Side Current @ VCPout = VCC/2
Phase Comparison Frequency
mA
mA
1
-1
fPD
MHz
8.184
IF Downconverter Block (f1stIFin = 61.38 MHz, f2ndLOin = 65.472 MHz, f2ndIF output = 4.092 MHz, ZS = 2kΩ, ZL = 2 kΩ)
NF2ndMIX
GV2ndMIX
VGC
Noise Figure of 2nd IF Mixer (SSB), (ZS = 50Ω)
Voltage Gain of 2nd Mixer/Amplifier, P1stIF = -50 dBm
Gain Control Voltage (Voltage at maximum gain)
dB
dB
V
12
47
0.5
DGC
Gain Control Range, P1stIF = -50 dBm
(Voltage at maximum gain)
dB
20
A2ndLO1stIF
A2ndLO2ndIF
2nd LO Isolation to 1st IF Input Pins, VAGC = 0 V
2nd LO Isolation to 2nd IF Output Pins, VAGC = 0 V
dB
dB
-70
-70
California Eastern Laboratories