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UPA1981TE-T1-A

更新时间： 2024-09-12 14:31:31
品牌 Logo 应用领域
日电电子 - NEC ISM频段开关光电二极管晶体管
页数 文件大小 规格书
4页 95K
描述
Small Signal Field-Effect Transistor, 2.8A I(D), 2-Element, N-Channel and P-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, MINIMOLD, SC-95, 3 PIN

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UPA1981TE-T1-A 技术参数

是否Rohs认证：符合生命周期：Transferred
包装说明：LEAD FREE, MINIMOLD, SC-95, 3 PINReach Compliance Code：compliant
风险等级：5.72Is Samacsys：N
配置：COMPLEX最大漏极电流 (ID)：2.8 A
最大漏源导通电阻：0.07 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：R-PDSO-G6JESD-609代码：e6
元件数量：2端子数量：6
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL AND P-CHANNEL
认证状态：Not Qualified表面贴装：YES
端子面层：TIN BISMUTH端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

UPA1981TE-T1-A 数据手册

 浏览型号UPA1981TE-T1-A的Datasheet PDF文件第2页浏览型号UPA1981TE-T1-A的Datasheet PDF文件第3页浏览型号UPA1981TE-T1-A的Datasheet PDF文件第4页 
DATA SHEET  
INTEGRATED LOAD SWITCH  
µ PA1981  
N-CHANNEL/P-CHANNEL MOS FET PAIR  
FOR LOAD SWITCH  
PACKAGE DRAWING (Unit: mm)  
DESCRIPTION  
+0.1  
+0.1  
–0.06  
0.32  
–0.05  
0.16  
The µ PA1981 is a N-Channel/P-Channel MOS FET pair for compact  
power management in portable electronic equipment where 2.5 to 8 V  
input and 2.8 A output current capability are needed.  
This load switch integrated a small N-Channel MOS FET (Q1), which  
drives a large P-Channel MOS FET (Q2) in one tiny package (SC-95).  
0 to 0.1  
0.65  
FEATURES  
0.95 0.95  
1.9  
• VS2D21 = 0.2 V MAX. (VS2S1 = 5.0 V, ID2 = −2.8 A, RD2S2(on)1 = 70 mΩ)  
0.9 to 1.1  
2.9 ±0.2  
• VS2D22 = 0.2 V MAX. (VS2S1 = 2.5 V, ID2 = −1.9 A, RD2S2(on)2 = 105 mΩ)  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
µ PA1981TE  
SC-95 (Mini Mold Thin Type)  
Marking: TZ  
PIN CONNECTION (Top View)  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Source2 to Source1 Input Voltage Range  
Gate1 to Source1 On Voltage Range  
Drain2 Current (DC) Note1  
VS2S1  
VG1S1  
ID2(DC)  
ID2(pulse)  
PT  
2.5 to 8.0  
1.5 to 7.0  
−2.8  
−10.0  
1.0  
V
V
A
6
5
4
1. S1(Q1)  
2. D2(Q2)  
3. D2(Q2)  
4. S2(Q2)  
Drain2 Current (pulse) Note2  
Total Power Dissipation Note1  
Channel Temperature  
A
5. G1(Q1)  
6. G2/D1  
W
°C  
°C  
Tch  
Tstg  
150  
−55 to +150  
Storage Temperature  
1
2
3
Notes 1. Mounted on FR-4 Board of 2500 mm2 x 1.6 mm, t ≤ 5 sec  
2. PW ≤ 10 µs, Duty Cycle ≤ 1%  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.  
When this device actually used, an additional protection circuit is externally required if a voltage exceeding  
the rated voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No. G17263EJ1V0DS00 (1st edition)  
Date Published July 2004 NS CP(K)  
Printed in Japan  
2004  
1234

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