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UPA1850GR-9JG

更新时间： 2024-09-23 22:26:03
品牌 Logo 应用领域
日电电子 - NEC 晶体晶体管功率场效应晶体管开关脉冲光电二极管
页数 文件大小 规格书
8页 67K
描述
P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING

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UPA1850GR-9JG 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：SMALL OUTLINE, R-PDSO-G8
针数：8Reach Compliance Code：compliant
ECCN代码：EAR99风险等级：5.92
Is Samacsys：N配置：SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：12 V最大漏极电流 (ID)：2.5 A
最大漏源导通电阻：0.2 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
元件数量：1端子数量：8
工作模式：ENHANCEMENT MODE封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：P-CHANNEL
最大脉冲漏极电流 (IDM)：10 A认证状态：Not Qualified
表面贴装：YES端子面层：TIN LEAD
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

UPA1850GR-9JG 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
PA1850  
µ
P-CHANNEL MOS FIELD EFFECT TRANSISTOR  
FOR SWITCHING  
DESCRIPTION  
The µPA1850 is a switching device which can be  
PACKAGE DRAWING (Unit : mm)  
-
driven directly by a 2.5 V power source.  
8
5
The µPA1850 features a low on-state resistance and  
excellent switching characteristics, and is suitable for  
applications such as power switch of portable machine  
and so on.  
1
:Drain1  
1.2 MAX.  
1.0±0.05  
2, 3 :Source1  
4
5
:Gate1  
:Gate2  
0.25  
6, 7 :Source2  
:Drain2  
8
FEATURES  
+5°  
–3°  
3°  
• Can be driven by a 2.5-V power source  
• Low on-state resistance  
0.5  
0.1±0.05  
+0.15  
–0.1  
0.6  
1
4
DS(on)1  
R
DS(on)2  
R
DS(on)3  
R
GS  
D
= 115 mΩ MAX. (V = –4.5 V, I = –1.5 A)  
GS  
D
= 130 mΩ MAX. (V = –4.0 V, I = –1.5 A)  
GS  
D
= 200 mΩ MAX. (V = –2.5 V, I = –1.5 A)  
6.4 ±0.2  
4.4 ±0.1  
3.15 ±0.15  
3.0 ±0.1  
• Built-in G-S protection diode against ESD  
1.0 ±0.2  
ORDERING INFORMATION  
PART NUMBER  
PACKAGE  
0.65  
0.8 MAX.  
0.1  
µPA1850GR-9JG  
Power TSSOP8  
+0.03  
–0.08  
0.27  
0.10 M  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
DSS  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current (DC)  
V
V
–12  
V
V
EQUIVALENT CIRCUIT  
GSS  
–10/+5  
Drain1  
Drain2  
D(DC)  
2.5  
I
A
#
Drain Current (pulse) Note1  
Total Power Dissipation Note2  
Channel Temperature  
Storage Temperature  
D(pulse)  
10  
I
A
#
Body  
Diode  
Body  
Diode  
T
P
2.0  
150  
W
°C  
°C  
Gate1  
Gate2  
ch  
T
stg  
T
–55 to +150  
Gate  
Gate  
Protection  
Diode  
Protection  
Diode  
Source1  
Source2  
Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1 %  
2. Mounted on ceramic substrate of 5000 mm2 x 1.1 mm  
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.  
When this device actually used, an additional protection circuit is externally required if a voltage  
exceeding the rated voltage may be applied to this device.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No.  
Date Published January 2000 NS CP(K)  
Printed in Japan  
D11818EJ2V0DS00 (2nd edition)  
The mark ★ shows major revised points.  
1997, 2000  
©
12345678

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