Datasheet > UL62H1708ASK55G1

UL62H1708ASK55G1

更新时间： 2023-01-02 20:54:30

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器光电二极管
页数	文件大小	规格书
10页	176K
描述
Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOP-32

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UL62H1708ASK55G1 数据手册

Preliminary

UL62H1708A

Low Voltage Automotive Fast 128K x 8 SRAM

Features

Description

! 131072 x 8 bit static CMOS RAM

! 35 and 55 ns Access Time

! Common data inputs and

data outputs

The UL62H1708A is a static RAM

available at the outputs DQ0-DQ7.

After the address change, the data

outputs go High-Z until the new

information is available. The data

outputs have no preferred state. If

the memory is driven by CMOS

levels in the active state, and if

there is no change of the address,

data input and control signals W or

G, the operating current (I_O= 0 mA)

drops to the value of the operating

current in the Standby mode. The

Read cycle is finished by the falling

edge of E2 or W, or by the rising

edge of E1, respectively.

manufactured using a CMOS pro-

cess technology with the following

operating modes:

! Three-state outputs

! Typ. operating supply current

35 ns: 45mA

- Read

- Write

- Standby

- Data Retention

The memory array is based on a

6-Transistor cell.

55 ns: 30mA

! Standby current <100µA at 125°C The circuit is activated by the rising

! TTL/CMOS-compatible

! Power supply voltage 3.3 V

! Operating temperature range

-40 °C to 85 °C

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active.

During the active state (E1 = L and

E2 = H) each address change

leads to a new Read cycle. In a

Read cycle, the data outputs are

activated by the falling edge of G,

afterwards the data word will be

-40 °C to 125 °C

! QS 9000 Quality Standard

! ESD protection > 2000 V

(MIL STD 883C M3015.7)

! Latch-up immunity >100 mA

! Package: SOP32 (450 mil)

TSOP I 32

Data retention is guaranteed down

to 2 V. With the exception of E1

and E2, all inputs consist of NOR

gates, so that no pull-up/pull-down

resistors are required.

sTSOP I 32

Pin Configuration

Pin Description

VCC

A15

n.c.

A16

A14

A12

A11

A10

A13

DQ7

DQ6

DQ5

DQ4

DQ3

Signal Name Signal Description

A13

A0 - A16

DQ0 - DQ7

Address Inputs

Data In/Out

A15

VCC

n.c.

A16

A14

A12

Chip Enable 1

Chip Enable 2

Output Enable

Write Enable

Power Supply Voltage

Ground

TSOP

SOP

A11

sTSOP

A10

VSS

DQ2

DQ7

DQ1

DQ0

VCC

VSS

n.c.

DQ0

DQ1

DQ2

VSS

DQ6

DQ5

DQ4

DQ3

not connected

Top View

April 21, 2004

12 3 4 5 6 7...10

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与UL62H1708ASK55G1相关器件

型号	品牌	获取价格	描述	数据表
UL62H1708AT1A55G1	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, LEAD FREE, STSOP1-32
UL62H1708AT1K35	CYPRESS	获取价格	Standard SRAM, 128KX8, 35ns, CMOS, PDSO32, STSOP1-32
UL62H1708AT1K35G1	CYPRESS	获取价格	128KX8 STANDARD SRAM, 35ns, PDSO32, LEAD FREE, STSOP1-32
UL62H1708ATA35	CYPRESS	获取价格	Standard SRAM, 128KX8, 35ns, CMOS, PDSO32, TSOP1-32
UL62H1708ATA35G1	CYPRESS	获取价格	128KX8 STANDARD SRAM, 35ns, PDSO32, LEAD FREE, TSOP1-32
UL62H1708ATA55	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, TSOP1-32
UL62H1708ATA55G1	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, LEAD FREE, TSOP1-32
UL62H1708ATK35	CYPRESS	获取价格	Standard SRAM, 128KX8, 35ns, CMOS, PDSO32, TSOP1-32
UL62H1708ATK55	CYPRESS	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, TSOP1-32
UL62H1708ATK55G1	CYPRESS	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, LEAD FREE, TSOP1-32

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