UL62H1616A
Low Voltage Automotive Fast 64K x 16 SRAM
Features
Description
! 65536 x 16 bit static CMOS RAM
! 15, 20 and 35 ns Access Time
! Common data inputs and
data outputs
The UL62H1616A is a static RAM
change leads to a new Read cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G. If LB = L the data lower byte will
be available at the outputs DQ0-
DQ7, on UB = L the data upper
byte appear at the outputs DQ8-
DQ15. After the address change,
the data outputs go High-Z until the
new information is available. The
data outputs have no preferred
state. The Read cycle is finished by
the falling edge of W, or by the
rising edge of E, respectively.
manufactured using a CMOS pro-
cess technology with the following
operating modes:
! Three-state outputs
- Lower / Upper Byte Read
- Word Read
! Standby current < 150 µA
at 125°C
- Lower / Upper Byte Write
- Word Write
! TTL/CMOS-compatible
! Power supply voltage 3.3 V
! Operating temperature range
K-Type:-40 °C to 85 °C
- Standby
- Data Retention
The memory array is based on a
6-Transistor cell.
A-Type:-40 °C to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity >100 mA
! Package: TSOP II 44 (400 mil)
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L and W = H each address
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Pin Configuration
Pin Description
BGA
A5
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
A6
A7
G
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
Signal Name Signal Description
LB
G
A0
A3
A1
A4
A6
A7
n.c.
A2
E
A0 - A15
Address Inputs
DQ8
UB
DQ0
DQ2
DQ0 - DQ15 Data In/Out
DQ9 DQ10 A5
VSS DQ11 n.c.
VCC DQ12 n.c.
DQ1
Chip Enable
E
E
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
W
A15
A14
A13
A12
n.c.
Output Enable
Write Enable
G
W
DQ3 VCC
9
n.c. DQ4 VSS
UB
LB
VCC
VSS
n.c.
Upper Byte Enable
Lower Byte Enable
Power Supply Voltage
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ14 DQ13 A14 A15 DQ5 DQ6
TSOPII
DQ15 n.c.
n.c. A8
A12 A13
A9 A10
W
DQ7
n.c.
A11
not connected
DQ9
DQ8
Top View
n.c.
A8
A9
A10
A11
n.c.
Top View
April 21, 2004
1