Datasheet > UL62H1616ATK15

UL62H1616ATK15

更新时间： 2023-01-03 08:24:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器光电二极管
页数	文件大小	规格书
10页	195K
描述
Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, TSOP2-44

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UL62H1616ATK15 数据手册

UL62H1616A

Low Voltage Automotive Fast 64K x 16 SRAM

Features

Description

! 65536 x 16 bit static CMOS RAM

! 15, 20 and 35 ns Access Time

! Common data inputs and

data outputs

The UL62H1616A is a static RAM

change leads to a new Read cycle.

In a Read cycle, the data outputs

are activated by the falling edge of

G. If LB = L the data lower byte will

be available at the outputs DQ0-

DQ7, on UB = L the data upper

byte appear at the outputs DQ8-

DQ15. After the address change,

the data outputs go High-Z until the

new information is available. The

data outputs have no preferred

state. The Read cycle is finished by

the falling edge of W, or by the

rising edge of E, respectively.

manufactured using a CMOS pro-

cess technology with the following

operating modes:

! Three-state outputs

- Lower / Upper Byte Read

- Word Read

! Standby current < 150 µA

at 125°C

- Lower / Upper Byte Write

- Word Write

! TTL/CMOS-compatible

! Power supply voltage 3.3 V

! Operating temperature range

K-Type:-40 °C to 85 °C

- Standby

- Data Retention

The memory array is based on a

6-Transistor cell.

A-Type:-40 °C to 125 °C

! QS 9000 Quality Standard

! ESD protection > 2000 V

(MIL STD 883C M3015.7)

! Latch-up immunity >100 mA

! Package: TSOP II 44 (400 mil)

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. During the active state

E = L and W = H each address

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

Pin Configuration

Pin Description

BGA

DQ15

DQ14

DQ13

DQ12

VSS

VCC

DQ11

DQ10

Signal Name Signal Description

n.c.

A0 - A15

Address Inputs

DQ8

DQ0

DQ2

DQ0 - DQ15 Data In/Out

DQ9 DQ10 A5

VSS DQ11 n.c.

VCC DQ12 n.c.

DQ1

Chip Enable

DQ0

DQ1

DQ2

DQ3

VCC

VSS

DQ4

DQ5

DQ6

DQ7

A15

A14

A13

A12

n.c.

Output Enable

Write Enable

DQ3 VCC

n.c. DQ4 VSS

VCC

VSS

n.c.

Upper Byte Enable

Lower Byte Enable

Power Supply Voltage

Ground

DQ14 DQ13 A14 A15 DQ5 DQ6

TSOPII

DQ15 n.c.

n.c. A8

A12 A13

A9 A10

DQ7

n.c.

A11

not connected

DQ9

DQ8

Top View

n.c.

A10

A11

n.c.

Top View

April 21, 2004

12 3 4 5 6 7...10

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