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SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005
D
Operation Down to an Input
Voltage of 1.8 V
simplified schematic block diagram and
application circuit
D
D
High Efficiency Boost, SEPIC or
Flyback (Buck-Boost) Topologies
1.8 V(MIN)
+
+
Drives External FETs for
High-Current Applications
VPUMP
VIN
2 CELL
ALKALINE/
NiCd OR
1 LI−ION
7
9
1.24 V
VREF
D
Up to 2-MHz Oscillator
CP
8
3
D
Synchronizable Fixed Frequency
Operation
SYNC/SD
RT
CHARGE
PUMP
13
14
VOUT
PWM
OSC
D
D
High-Efficiency Low-Power Mode
RSEN
RECT
2
VOUT
VPUMP
High-Efficiency at Very Low-Power
with Programmable Variable
Frequency Mode
4
RSEL
ANTI−
CROSS
COND.
19
6
D
D
D
D
D
D
Pulse-by-Pulse Current Limit
VGD
CHRG
5-µA Supply Current in Shutdown
150-µA Supply Current in Sleep
Mode
PWM CIRCUITRY
CURRENT LIMIT
ISENSE
PGND
12
5
+
X10
Selectable NMOS or PMOS
Rectification
50 mV TYP
LOW POWER
MODE
1.24 V
ERROR
AMP
Built-In Power-On Reset
(UCC39422 Only)
SLOPE
+
COMPENSATION
FB
17
18
16
PFM MODE
CONTROL
Built-In Low-Voltage Detect
(UCC39422 Only)
COMP
PFM
GND
15
+
description
1.22V
The UCC39421 family of synchronous
RESET
UCC39422
ONLY
1
PWM controllers is optimized to operate
from dual alkaline/NiCd cells or a single
Lithium-Ion (Li-Ion) cell, and convert to
adjustable output voltages from 2.5 V to
8 V. For applications where the input
voltage does not exceed the output, a
standard boost configuration is used.
200 mS
RESET/
POR
+
1.18 V
RSADJ
VDET
LOWBAT
20
11
10
+
1.24 V
UDG−98122
For other applications where the input voltage can swing above and below the output, a 1:1 coupled inductor
(Flyback or SEPIC) is used in place of the single inductor. Fixed frequency operation can be programmed, or
synchronized to an external clock source. In applications where (at light loads) variable frequency mode is
acceptable, the IC can be programmed to automatically enter PFM (pulse frequency modulation) mode for an
additional efficiency benefit.
Synchronous rectification provides excellent efficiency at high power levels, where N- or P- type MOSFETs can
be used. At lower power levels (between 10% and 20% of full load) where fixed frequency operation is required,
low power mode is entered. This mode optimizes efficiency by cutting back on the gate drive of the charging
FET. At very low power levels, the IC enters a variable frequency mode (PFM). PFM can be disabled by the user.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2000, Texas Instruments Incorporated
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