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UCC28050DR PDF预览

UCC28050DR

更新时间： 2024-11-30 04:48:15
品牌 Logo 应用领域
德州仪器 - TI 稳压器开关式稳压器或控制器电源电路开关式控制器功率因数校正光电二极管信息通信管理
页数 文件大小 规格书
28页 446K
描述
TRANSITION MODE PFC CONTRLLER

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中文翻译

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UCC28050DR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：GREEN, PLASTIC, MS-012AA, SOIC-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.68Is Samacsys：N
模拟集成电路 - 其他类型：POWER FACTOR CONTROLLER控制模式：CURRENT-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：18 V
最小输入电压：10 V标称输入电压：12 V
JESD-30 代码：R-PDSO-G8JESD-609代码：e4
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
最大输出电流：0.75 A封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.58 mm子类别：Switching Regulator or Controllers
最大供电电流 (Isup)：4 mA最大供电电压 (Vsup)：18 V
表面贴装：YES切换器配置：BOOST
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.91 mm
Base Number Matches：1

UCC28050DR 数据手册

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CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K  
Synchronous Dual-Port RAM  
x 36 and 128K/256K x 18  
CY7C0837V  
CY7C0830V/CY7C0831V  
CY7C0832V/CY7C0833V  
PRELIMINARY  
TM  
FLEx18 3.3V 32K/64K/128K/256K/512K x 18  
Synchronous Dual-Port RAM  
Functional Description  
Features  
• True dual-ported memory cells that allow simultaneous  
access of the same memory location  
• Synchronous pipelined operation  
• Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit  
devices  
• Pipelined output mode allows fast operation  
• 0.18-micron CMOS for optimum speed and power  
• High-speed clock to data access  
• 3.3V low power  
The FLEx18 family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit  
and 9-Mbit pipelined, synchronous, true dual-port static RAMs  
that are high-speed, low-power 3.3V CMOS. Two ports are  
provided, permitting independent, simultaneous access to any  
location in memory. The result of writing to the same location  
by more than one port at the same time is undefined. Registers  
on control, address, and data lines allow for minimal set-up  
and hold time.  
During a Read operation, data is registered for decreased  
cycle time. Each port contains a burst counter on the input  
address register. After externally loading the counter with the  
initial address, the counter will increment the address inter-  
nally (more details to follow). The internal Write pulse width is  
independent of the duration of the R/W input signal. The  
internal Write pulse is self-timed to allow the shortest possible  
cycle times.  
—Active as low as 225 mA (typ)  
— Standby as low as 55 mA (typ)  
• Mailbox function for message passing  
• Global master reset  
• Separate byte enables on both ports  
• Commercial and industrial temperature ranges  
• IEEE 1149.1-compatible JTAG boundary scan  
• 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)  
• 120TQFP (14 mm x 14 mm x 1.4 mm)  
• Counter wrap around control  
A HIGH on CE0 or LOW on CE1 for one clock cycle will power  
down the internal circuitry to reduce the static power  
consumption. One cycle with chip enables asserted is required  
to reactivate the outputs.  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap-around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
— Internal mask register controls counter wrap-around  
— Counter-interrupt flags to indicate wrap-around  
— Memory block retransmit operation  
• Counter readback on address lines  
• Mask register readback on address lines  
• Dual Chip Enables on both ports for easy depth  
expansion  
The CY7C0833V device in this family has limited features.  
Please see Address Counter and Mask Register  
Operations[15] on page 6 for details.  
Table 1. Product Selection Guide  
Density  
512-Kbit  
(32K x 18)  
1-Mbit  
(64K x 18)  
2-Mbit  
(128K x 18)  
4-Mbit  
(256K x 18)  
9-Mbit  
(512K x 18)  
Part Number  
CY7C0837V  
167  
CY7C0830V  
CY7C0831V  
CY7C0832V  
CY7C0833V  
133  
Max. Speed (MHz)  
167  
4.0  
167  
4.0  
167  
4.0  
Max. Access Time - clock to Data (ns)  
Typical operating current (mA)  
Package  
4.0  
4.7  
225  
225  
225  
225  
270  
144 FBGA  
120 TQFP  
144 FBGA  
120 TQFP  
144 FBGA  
120 TQFP  
144 FBGA  
144 FBGA  
Cypress Semiconductor Corporation  
Document #: 38-06059 Rev. *K  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
July 06, 2004  
1234567...28

中文翻译

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UCC28050DR 替代型号

型号 品牌 替代类型 描述 数据表
UCC28050D TI

完全替代

 TRANSITION MODE PFC CONTRLLER
UCC28051DR TI

类似代替

 TRANSITION MODE PFC CONTRLLER
UCC38050P TI

类似代替

 TRANSITION MODE PFC CONTRLLER

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