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UC3843W PDF预览

UC3843W

更新时间: 2024-01-18 14:20:52
品牌 Logo 应用领域
其他 - ETC 控制器
页数 文件大小 规格书
8页 579K
描述
SMPS Controller

UC3843W 技术参数

生命周期:Obsolete包装说明:DIE,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.64
模拟集成电路 - 其他类型:SWITCHING CONTROLLER控制模式:CURRENT-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:30 V
JESD-30 代码:X-XUUC-N8功能数量:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出电流:1 A
标称输出电压:2.5 V封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:UNSPECIFIED
封装形式:UNCASED CHIP认证状态:Not Qualified
最大供电电流 (Isup):25 mA表面贴装:YES
切换器配置:SINGLE最大切换频率:500 kHz
技术:BIPOLAR温度等级:COMMERCIAL
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

UC3843W 数据手册

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application  
INFO  
UC1842/3/4/5  
UC2842/3/4/5  
UC3842/3/4/5  
available  
Current Mode PWM Controller  
FEATURES  
DESCRIPTION  
Optimized For Off-line And DC  
To DC Converters  
The UC1842/3/4/5 family of control ICs provides the necessary features to  
implement off-line or DC to DC fixed frequency current mode control schemes  
with a minimal external parts count. Internally implemented circuits include  
under-voltage lockout featuring start up current less than 1mA, a precision  
reference trimmed for accuracy at the error amp input, logic to insure latched  
operation, a PWM comparator which also provides current limit control, and a  
totem pole output stage designed to source or sink high peak current. The  
output stage, suitable for driving N Channel MOSFETs, is low in the off state.  
Low Start Up Current (<1mA)  
Automatic Feed Forward  
Compensation  
Pulse-by-pulse Current Limiting  
Enhanced Load Response  
Characteristics  
Differences between members of this family are the under-voltage lockout  
thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have  
UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line  
applications. The corresponding thresholds for the UC1843 and UC1845 are  
8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles  
approaching 100%. A range of zero to 50% is obtained by the UC1844 and  
UC1845 by the addition of an internal toggle flip flop which blanks the output  
off every other clock cycle.  
Under-voltage Lockout With  
Hysteresis  
Double Pulse Suppression  
High Current Totem Pole  
Output  
Internally Trimmed Bandgap  
Reference  
500khz Operation  
Low RO Error Amp  
BLOCK DIAGRAM  
A/B  
Note 1:  
Note 2:  
A = DIL-8 Pin Number. B = SO-14 and CFP-14 Pin Number.  
Toggle flip flop used only in 1844 and 1845.  
SLUS223A - APRIL 1997 - REVISED MAY 2002  

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