UC3842DW

更新时间： 2024-09-27 13:15:07

品牌	Logo	应用领域
德州仪器 - TI		控制器
页数	文件大小	规格书
8页	435K
描述
1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO16

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技术参数
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UC3842DW 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.64
Is Samacsys：	N	模拟集成电路 - 其他类型：	SWITCHING CONTROLLER
控制模式：	CURRENT-MODE	控制技术：	PULSE WIDTH MODULATION
最大输入电压：	25 V	最小输入电压：	11.5 V
JESD-30 代码：	R-PDSO-G16	长度：	10.365 mm
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
最大输出电流：	1 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
座面最大高度：	2.64 mm	表面贴装：	YES
切换器配置：	SINGLE	最大切换频率：	500 kHz
技术：	BIPOLAR	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.5 mm
Base Number Matches：	1

UC3842DW 数据手册

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

Current Mode PWM Controller

FEATURES

DESCRIPTION

•

Optimized For Off-line And DC

To DC Converters

The UC1842/3/4/5 family of control ICs provides the necessary features to im-

plement off-line or DC to DC fixed frequency current mode control schemes

with a minimal external parts count. Internally implemented circuits include un-

der-voltage lockout featuring start up current less than 1mA, a precision refer-

ence trimmed for accuracy at the error amp input, logic to insure latched

operation, a PWM comparator which also provides current limit control, and a

totem pole output stage designed to source or sink high peak current. The out-

put stage, suitable for driving N Channel MOSFETs, is low in the off state.

•

Low Start Up Current (<1mA)

Automatic Feed Forward

Compensation

•

Pulse-by-pulse Current Limiting

Enhanced Load Response

Characteristics

Differences between members of this family are the under-voltage lockout

thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have

UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applica-

tions. The corresponding thresholds for the UC1843 and UC1845 are 8.4V

and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching

100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the

addition of an internal toggle flip flop which blanks the output off every other

clock cycle.

•

Under-voltage Lockout With

Hysteresis

•

Double Pulse Suppression

High Current Totem Pole

Output

•

Internally Trimmed Bandgap

Reference

•

500khz Operation

Low RO Error Amp

BLOCK DIAGRAM

Note 1: A/B A = DIL-8 Pin Number. B = SO-14 Pin Number.

Note 2: Toggle flip flop used only in 1844 and 1845.

4/97

12 3 4 5 6 7 8

中文翻译

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