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UC3823AL PDF预览

UC3823AL

更新时间: 2024-02-25 12:12:12
品牌 Logo 应用领域
其他 - ETC 模拟IC开关
页数 文件大小 规格书
9页 318K
描述
Analog IC

UC3823AL 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ, LDCC20,.4SQ针数:20
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.66Is Samacsys:N
其他特性:CAN ALSO BE CONFIGURED IN CURRENT MODE模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制模式:VOLTAGE-MODE控制技术:PULSE WIDTH MODULATION
最大输入电压:30 V最小输入电压:10 V
标称输入电压:15 VJESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.965 mm
湿度敏感等级:2功能数量:1
端子数量:20最高工作温度:70 °C
最低工作温度:最大输出电流:2 A
标称输出电压:5.1 V封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Switching Regulator or Controllers
表面贴装:YES切换器配置:SINGLE
最大切换频率:1000 kHz技术:BIPOLAR
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.965 mmBase Number Matches:1

UC3823AL 数据手册

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application  
INFO  
UC1823A,B/1825A,B  
UC2823A,B/2825A,B  
UC3823A,B/3825A,B  
available  
High Speed PWM Controller  
FEATURES  
DESCRIPTION  
Improved versions of the  
UC3823/UC3825 PWMs  
The UC3823A & B and the UC3825A & B family of PWM control ICs are  
improved versions of the standard UC3823 & UC3825 family. Performance  
enhancements have been made to several of the circuit blocks. Error ampli-  
fier gain bandwidth product is 12MHz while input offset voltage is 2mV. Cur-  
rent limit threshold is guaranteed to a tolerance of 5%. Oscillator discharge  
current is specified at 10mA for accurate dead time control. Frequency ac-  
curacy is improved to 6%. Startup supply current, typically 100µA, is ideal  
for off-line applications. The output drivers are redesigned to actively sink  
current during UVLO at no expense to the startup current specification. In  
addition each output is capable of 2A peak currents during transitions.  
Compatible with Voltage or  
Current-Mode Topologies  
Practical Operation at Switching  
Frequencies to 1MHz  
50ns Propagation Delay to Output  
High Current Dual Totem Pole  
Outputs (2A Peak)  
Functional improvements have also been implemented in this family. The  
UC3825 shutdown comparator is now a high-speed overcurrent comparator  
with a threshold of 1.2V. The overcurrent comparator sets a latch that en-  
sures full discharge of the soft start capacitor before allowing a restart.  
While the fault latch is set, the outputs are in the low state. In the event of  
continuous faults, the soft start capacitor is fully charged before discharge  
to insure that the fault frequency does not exceed the designed soft start  
period. The UC3825 Clock pin has become CLK/LEB. This pin combines  
the functions of clock output and leading edge blanking adjustment and has  
been buffered for easier interfacing.  
Trimmed Oscillator Discharge Current  
Low 100µA Startup Current  
Pulse-by-Pulse Current Limiting  
Comparator  
Latched Overcurrent Comparator With  
Full Cycle Restart  
(continued)  
BLOCK DIAGRAM  
UDG-95101  
* Note: 1823A,B Version Toggles Q and Q are always low  
SLUS334A - AUGUST 1995 - REVISED NOVEMBER 2000  

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