Datasheet > UC3714DP

UC3714DP

更新时间： 2024-02-29 07:47:41

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描述
Dual Peripheral Driver

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数据手册

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UC3714DP 数据手册

application

INFO

UC1714/5

UC2714/5

UC3714/5

available

Complementary Switch FET Drivers

FEATURES

DESCRIPTION

• Single Input (PWM and TTL

These two families of high speed drivers are designed to provide drive

waveforms for complementary switches. Complementary switch configura-

tions are commonly used in synchronous rectification circuits and active

clamp/reset circuits, which can provide zero voltage switching. In order to

facilitate the soft switching transitions, independently programmable delays

between the two output waveforms are provided on these drivers. The de-

lay pins also have true zero voltage sensing capability which allows imme-

diate activation of the corresponding switch when zero voltage is applied.

These devices require a PWM-type input to operate and can be interfaced

with commonly available PWM controllers.

Compatible)

• High Current Power FET Driver, 1.0A

Source/2A Sink

• Auxiliary Output FET Driver, 0.5A

Source/1A Sink

• Time Delays Between Power and

Auxiliary Outputs Independently

Programmable from 50ns to 500ns

In the UC1714 series, the AUX output is inverted to allow driving a

p-channel MOSFET. In the UC1715 series, the two outputs are configured

in a true complementary fashion.

• Time Delay or True Zero-Voltage

Operation Independently Configurable

for Each Output

• Switching Frequency to 1MHz

• Typical 50ns Propagation Delays

• ENBL Pin Activates 220µA Sleep

Mode

• Power Output is Active Low in Sleep

Mode

• Synchronous Rectifier Driver

BLOCK DIAGRAM

PWR

50ns –500ns

TIMER

INPUT

UC1714

ONLY

REF

AUX

VCC

50ns –500ns

TIMER

BIAS

ENBL

LOGIC

GATES

REF

TIMER

REF

GND

1.4V

ENBL

ENABLE

Note: Pin numbers refer to J, N and D packages.

UDG-99028

SLUS170A - FEBRUARY 1999 - REVISED JANUARY 2002

12 3 4 5 6 7 8

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