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UC37136M PDF预览

UC37136M

更新时间： 2024-02-28 08:54:39
品牌 Logo 应用领域
德州仪器 - TI 开关接口集成电路光电二极管输出元件驱动
页数 文件大小 规格书
9页 204K
描述
DUAL OUTPUT SWITCH

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中文翻译

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UC37136M 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SSOP, SSOP16,.25
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.73驱动器位数：2
接口集成电路类型：BUFFER OR INVERTER BASED PERIPHERAL DRIVERJESD-30 代码：R-PDSO-G16
端子数量：16最高工作温度：70 °C
最低工作温度：输出电流流向：SINK
最大输出电流：0.25 A标称输出峰值电流：1.1 A
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：25 V认证状态：Not Qualified
子类别：Peripheral Drivers标称供电电压：25 V
表面贴装：YES技术：BIPOLAR
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

UC37136M 数据手册

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SLUS447 - FEBRUARY 2000 - REVISED JULY 2000  
D
250-mA Continuous Total Output Drive  
DP, M, OR NP  
PACKAGES  
(TOP VIEW)  
D
D
D
D
Two Output Power Switches, 35-V  
Maximum Operation  
Low-Side or High-Side Switch  
Configuration  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
SD  
LS2  
N/C  
User Programmable Phasing of Output  
Switch LS2/HS2  
CDEL  
GND  
GND  
INV2  
IN2  
HS2  
GND  
GND  
HS1  
N/C  
Internal Output Voltage Clamp for Driving  
Inductive Loads  
D
D
D
D
9 V to 35 V Supply Voltage Range  
Current Limit Protection  
IN1  
LS1  
Thermal Shutdown Protection  
UVLO With User Programmable Time Delay  
description  
The UCx7136 bipolar dual switch contains all the control and drive circuitry required to drive resistive,  
capacitive, and inductive loads as in industrial sensor applications. The output drivers are 250-mA NPN power  
switches that can switch a load between a voltage supply up to 35 V and GND with a continuous output current  
rating of 250 mA, combined or individually. Internal 46-V Zener clamps are provided to clamp collector-to-emitter  
NPN power switch voltages to safe levels when driving inductive loads. The two outputs can be configured in  
any combination of high side (load to GND) or low side (load to VCC). The output of switch 1 is fixed in phase  
with the CMOS compatible IN1 pin. The CMOS compatible exclusive OR gate inputs, IN2 and INV2, determine  
the output phase of switch 2. An under voltage lockout (UVLO) function is provided to disable both output NPN  
power switches until VCC is greater than 8 V. Both output NPN power switches can also be disabled past the  
UVLO enable trip point by an external user programmable time delay capacitor. An internal current limit function  
enables a low on/off duty cycle of the NPN power switches should the dc current go beyond 1 A. An internal  
thermal shutdown function disables the switches if the IC temperature reaches 155°C such as in an overcurrent  
condition.  
schematic  
VCC  
1
3
REFERENCE  
REF  
15 N/C  
10 N/C  
16 LS2  
REF  
8 V  
µ
A
2.5  
UVLO  
CDEL  
5 k  
4 V  
Ω
S
R
Q
SWITCH 2  
CURRENT LIMIT  
0.7  
Ω
HS2  
LS1  
14  
9
155°C/135°C  
SD  
2
6
SWITCH 1  
INV2  
0.7  
Ω
11 HS1  
IN2  
IN1  
7
8
UDG-99016  
4
5
12  
13  
GND  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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