Preliminary
U636H04
PowerStore 512 x 8 nvSRAM
The SRAM can be read and written
an unlimited number of times, while
Features
Description
independent nonvolatile date resi-
des in EEPROM.
The U636H04 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
High-performance CMOS non-
volatile static RAM 512 x 8 bits
25 and 45 ns Access Times
12 and 25 ns Output Enable
Access Times
The U636H04 has two separate
modes of operation: SRAM mode
and nonvolatile mode.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
ICC = 15 mA at 200 ns Cycle Time nonvolatile operation, data is trans-
Unlimited Read and Write to
SRAM
Automatic STORE to EEPROM
on Power Down using system
capacitance
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM.
In this mode SRAM functions are
disabled.
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Unlimited RECALL cycles from
EEPROM
Single 5 V ± 10 % Operation
Operating temperature ranges:
0 to 70 °C
The U636H04 is a fast static RAM
(25 and 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. Data
transfers from the SRAM to the
EEPROM (the STORE operation)
take place automatically upon
power down using charge stored in
system capacitance. Transfers
from the EEPROM to the SRAM
(the RECALL operation) take place
automatically on power up.
-40 to 85 °C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
Packages: PDIP24 (600 mil)
SOP24 (300 mil)
Pin Configuration
Pin Description
VCC
A8
n.c.
W
1
24
A7
A6
A5
A4
A3
A2
A1
2
23
22
21
20
19
18
Signal Name Signal Description
3
4
A0 - A8
Address Inputs
Data In/Out
G
5
DQ0 - DQ7
n.c.
E
6
PDIP
SOP
Chip Enable
E
7
Output Enable
Write Enable
Power Supply Voltage
Ground
G
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
DQ1
DQ2
VSS
8
17
16
15
14
13
W
9
VCC
VSS
10
11
12
Top View
1
December 12, 1997