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U635H256SC25 PDF预览

U635H256SC25

更新时间: 2024-02-10 16:52:12
品牌 Logo 应用领域
SIMTEK 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
14页 258K
描述
Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.330 INCH, SOP1-28

U635H256SC25 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP28,.5Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.11最长访问时间:25 ns
备用内存宽度:1JESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:18.1 mm
内存密度:262144 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.5
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
座面最大高度:2.54 mm最大待机电流:0.04 A
子类别:SRAMs最大压摆率:0.095 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.75 mm
Base Number Matches:1

U635H256SC25 数据手册

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U635H256  
PowerStore 32K x 8 nvSRAM  
Not Recommended For New Designs  
Features  
Description  
‡
The U635H256 has two separate  
modes of operation: SRAM mode  
and nonvolatile mode. In SRAM  
mode, the memory operates as an  
ordinary static RAM. In nonvolatile  
operation, data is transferred in  
parallel from SRAM to EEPROM or  
from EEPROM to SRAM. In this  
mode SRAM functions are disab-  
led.  
The U635H256 is a fast static RAM  
(25 ns), with a nonvolatile electri-  
cally erasable PROM (EEPROM)  
element incorporated in each static  
memory cell. The SRAM can be  
read and written an unlimited num-  
ber of times, while independent  
High-performance CMOS non  
volatile static RAM 32768 x 8 bits  
25 ns Access Time  
10 ns Output Enable Access  
grity.  
STORE cycles also may be initia-  
ted under user control via a soft-  
ware sequence.  
‡
‡
Time  
Once a STORE cycle is initiated,  
further input or output are disabled  
until the cycle is completed.  
Because a sequence of addresses  
is used for STORE initiation, it is  
important that no other read or  
write accesses intervene in the  
sequence or the sequence will be  
aborted.  
RECALL cycles may also be initia-  
ted by a software sequence.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
cleared and second, the nonvola-  
tile information is transferred into  
the SRAM cells.  
‡
ICC = 15 mA typ. at 200 ns Cycle  
Time  
‡
Automatic STORE to EEPROM  
on Power Down using system  
capacitance  
Software initiated STORE  
Automatic STORE Timing  
106 STORE cycles to EEPROM  
100 years data retention in  
EEPROM  
Automatic RECALL on Power Up  
Software RECALL Initiation  
Unlimited RECALL cycles from  
EEPROM  
‡
‡
‡
‡
‡
‡
‡
nonvolatile  
data  
resides  
in  
EEPROM. Data transfers from the  
SRAM to the EEPROM (the  
STORE operation) take place auto-  
matically upon power down using  
charge stored in system capaci-  
‡
‡
Single 5 V ± 10 % Operation  
Operating temperature range:  
0 to 70 °C  
The RECALL operation in no way  
alters the data in the EEPROM  
cells. The nonvolatile data can be  
recalled an unlimited number of  
times.  
-40 to 85°C  
‡
‡
tance.  
Transfers  
from  
the  
QS 9000 Quality Standard  
ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
RoHS compliance and Pb- free  
Package: SOP28 (330 mil)  
EEPROM to the SRAM (the  
RECALL operation) take place  
automatically on power up. The  
U635H256 combines the high per-  
The U635H256 is pin compatible  
with standard SRAMs.  
‡
formance and ease of use of a fast  
SRAM with nonvolatile data inte-  
Pin Description  
Pin Configuration  
A14  
A12  
A7  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
W
2
3
A13  
A8  
A6  
4
Signal Name Signal Description  
A5  
5
A9  
A0 - A14  
Address Inputs  
Data In/Out  
A4  
6
A11  
G
DQ0 - DQ7  
A3  
7
Chip Enable  
E
SOP  
A2  
8
A10  
E
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
G
A1  
9
W
A0  
10  
11  
12  
13  
14  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
VCC  
VSS  
DQ0  
DQ1  
DQ2  
VSS  
Top View  
August 15, 2006  
STK Control #ML0051  
1
Rev 1.1  

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