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U635H256D1C45 PDF预览

U635H256D1C45

更新时间: 2024-01-09 12:19:48
品牌 Logo 应用领域
SIMTEK 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
13页 208K
描述
Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28

U635H256D1C45 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP28,.6针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.15
最长访问时间:45 ns备用内存宽度:1
JESD-30 代码:R-PDIP-T28JESD-609代码:e0
长度:37.1 mm内存密度:262144 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
功能数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP28,.6封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:5.1 mm
最大待机电流:0.033 A子类别:SRAMs
最大压摆率:0.065 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15.24 mm

U635H256D1C45 数据手册

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U635H256  
PowerStore 32K x 8 nvSRAM  
Features  
Description  
The U635H256 has two separate  
modes of operation: SRAM mode  
and nonvolatile mode. In SRAM  
mode, the memory operates as an  
ordinary static RAM. In nonvolatile  
operation, data is transferred in  
parallel from SRAM to EEPROM or  
from EEPROM to SRAM. In this  
mode SRAM functions are disab-  
led.  
S High-performance CMOS non-  
volatile static RAM 32768 x 8 bits  
S 25, 35 and 45 ns Access Times  
S 10, 15 and 20 ns Output Enable  
Access Times  
grity.  
STORE cycles also may be initia-  
ted under user control via a soft-  
ware sequence.  
Once a STORE cycle is initiated,  
further input or output are disabled  
until the cycle is completed.  
Because a sequence of addresses  
is used for STORE initiation, it is  
important that no other read or  
write accesses intervene in the  
sequence or the sequence will be  
aborted.  
S ICC = 15 mA typ. at 200 ns Cycle  
Time  
S Automatic STORE to EEPROM  
on Power Down using system  
capacitance  
The U635H256 is a fast static RAM  
(25, 35, 45 ns), with a nonvolatile  
S Software initiated STORE  
S Automatic STORE Timing  
S 106 STORE cycles to EEPROM  
S 100 years data retention in  
EEPROM  
electrically  
erasable  
PROM  
(EEPROM) element incorporated  
in each static memory cell. The  
SRAM can be read and written an  
unlimited number of times, while  
independent nonvolatile data resi-  
des in EEPROM. Data transfers  
from the SRAM to the EEPROM  
(the STORE operation) take place  
automatically upon power down  
using charge stored in system  
capacitance. Transfers from the  
EEPROM to the SRAM (the  
RECALL operation) take place  
automatically on power up. The  
U635H256 combines the high per-  
RECALL cycles may also be initia-  
ted by a software sequence.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
cleared and second, the nonvola-  
tile information is transferred into  
the SRAM cells.  
S Automatic RECALL on Power Up  
S Software RECALL Initiation  
S Unlimited RECALL cycles from  
EEPROM  
S Single 5 V ± 10 % Operation  
S Operating temperature range:  
0 to 70 °C  
The RECALL operation in no way  
alters the data in the EEPROM  
cells. The nonvolatile data can be  
recalled an unlimited number of  
times.  
The U635H256 is pin compatible  
with standard SRAMs.  
-40 to 85 °C  
S QS 9000 Quality Standard  
S ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
S RoHS compliance and Pb- free  
S Packages: PDIP28 (300 mil)  
PDIP28 (600 mil)  
formance and ease of use of a fast  
SOP28 (330 mil)  
SRAM with nonvolatile data inte-  
Pin Description  
Pin Configuration  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
W
A13  
A8  
A9  
A11  
G
Signal Name Signal Description  
A0 - A14  
DQ0 - DQ7  
Address Inputs  
Data In/Out  
PDIP  
SOP  
Chip Enable  
E
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
A10  
E
G
W
VCC  
VSS  
9
A0  
10  
11  
12  
13  
14  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ0  
DQ1  
DQ2  
VSS  
Top View  
1
April 7, 2005  

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