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U633H04SC45G1 PDF预览

U633H04SC45G1

更新时间： 2023-08-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管
页数 文件大小 规格书
13页 202K
描述
512X8 NON-VOLATILE SRAM, 45ns, PDSO28, 0.300 INCH, SOP-28

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U633H04SC45G1 数据手册

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Preliminary  
U633H04  
PowerStore 512 x 8 nvSRAM  
Features  
Description  
The U633H04 combines the high  
performance and ease of use of a  
fast SRAM with nonvolatile data  
integrity.  
STORE cycles also may be initiated  
under user control via a single pin  
(HSB).  
High-performance CMOS non-  
volatile static RAM 512 x 8 bits  
25 and 45 ns Access Times  
12 and 25 ns Output Enable  
Access Times  
The U633H04 has two separate  
modes of operation: SRAM mode  
and nonvolatile mode. In SRAM  
mode, the memory operates as an  
ordinary static RAM. In nonvolatile  
Once a STORE cycle is initiated,  
further input or output are disabled  
until the cycle is completed.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
cleared and second, the nonvolatile  
information is transferred into the  
SRAM cells.  
The RECALL operation in no way  
alters the data in the EEPROM  
cells. The nonvolatile data can be  
recalled an unlimited number of  
times.  
ICC = 15 mA at 200 ns Cycle Time operation, data is transferred in  
Unlimited Read and Write to  
SRAM  
Automatic STORE to EEPROM  
on Power Down using external  
capacitor  
Hardware initiated STORE  
(STORE Cycle Time < 10 ms)  
Automatic STORE Timing  
105 STORE cycles to EEPROM  
10 years data retention in  
EEPROM  
Automatic RECALL on Power Up  
Unlimited RECALL cycles from  
EEPROM  
parallel from SRAM to EEPROM or  
from EEPROM to SRAM. In this  
mode SRAM functions are disab-  
led.  
The U633H04 is a fast static RAM  
(25 and 45 ns), with a nonvolatile  
electrically  
erasable  
PROM  
(EEPROM) element incorporated  
in each static memory cell. The  
SRAM can be read and written an  
unlimited number of times, while  
independent nonvolatile data resi-  
des in EEPROM.  
Data transfers from the SRAM to  
the EEPROM (the STORE opera-  
tion) take place automatically upon  
power down using charge stored in  
an external 100 µF capacitor.  
Transfers from the EEPROM to the  
SRAM (the RECALL operation)  
take place automatically on power  
up.  
Single 5 V ± 10 % Operation  
Operating temperature ranges:  
0 to 70 °C  
-40 to 85 °C  
CECC 90000 Quality Standard  
ESD characterization according  
MIL STD 883C M3015.7-HBM  
Packages: PDIP28 (300 mil)  
PDIP28 (600 mil)  
SOP28 (300 mil)  
Pin Configuration  
Pin Description  
VCCX  
W
1
VCAP  
n.c.  
A7  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
2
HSB  
A8.  
Signal Name Signal Description  
3
4
A6  
A0 - A8  
Address Inputs  
Data In/Out  
n.c.  
n.c.  
G
5
A5  
DQ0 - DQ7  
6
A4  
Chip Enable  
E
7
PDIP  
SOP  
A3  
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
G
n.c.  
E
8
A2  
W
9
A1  
VCCX  
VSS  
VCAP  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
10  
11  
12  
13  
14  
A0  
DQ0  
DQ1  
DQ2  
VSS  
Capacitor  
Hardware Store/Busy  
HSB  
Top View  
December 12, 1997  
1
1234567...13

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