U632H64
PowerStore 8K x 8 nvSRAM
Features
Description
S High-performance CMOS non-
volatile static RAM 8192 x 8 bits
S 25, 35 and 45 ns Access Times
S 12, 20 and 25 ns Output Enable
Access Times
The U632H64 has two separate ware sequence or via a single pin
modes of operation: SRAM mode (HSB).
and nonvolatile mode. In SRAM Once a STORE cycle is initiated,
mode, the memory operates as an further input or output are disabled
ordinary static RAM. In nonvolatile until the cycle is completed.
S ICC = 15 mA at 200 ns Cycle Time operation, data is transferred in Because a sequence of addresses
S Automatic STORE to EEPROM
on Power Down using external
capacitor
parallel from SRAM to EEPROM or is used for STORE initiation, it is
from EEPROM to SRAM. In this important that no other read or
mode SRAM functions are disab- write accesses intervene in the
S Hardware or Software initiated
STORE
led.
sequence or the sequence will be
The U632H64 is a fast static RAM aborted.
(STORE Cycle Time < 10 ms)
S Automatic STORE Timing
S 105 STORE cycles to EEPROM
S 10 years data retention in
EEPROM
(25, 35, 45 ns), with a nonvolatile RECALL cycles may also be initia-
electrically
erasable
PROM ted by a software sequence.
(EEPROM) element incorporated Internally, RECALL is a two step
in each static memory cell. The procedure. First, the SRAM data is
SRAM can be read and written an cleared and second, the nonvola-
unlimited number of times, while tile information is transferred into
independent nonvolatile data resi- the SRAM cells.
des in EEPROM. Data transfers The RECALL operation in no way
from the SRAM to the EEPROM alters the data in the EEPROM
(the STORE operation) take place cells. The nonvolatile data can be
automatically upon power down recalled an unlimited number of
using charge stored in an external times.
S Automatic RECALL on Power Up
S Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
S Unlimited RECALL cycles from
EEPROM
S Single 5 V ± 10 % Operation
S Operating temperature ranges:
0 to 70 °C
100 µF capacitor. Transfers from
-40 to 85 °C
the EEPROM to the SRAM (the
S QS 9000 Quality Standard
S ESD characterization according
MIL STD 883C M3015.7-HB
(classification see IC Code
Numbers)
RECALL operation) take place
automatically on power up. The
U632H64 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
S RoHS compliance and Pb- free
S Packages:PDIP28 (600 mil)
SOP28 (330 mil)
grity.
STORE cycles also may be initia-
ted under user control via a soft-
Pin Configuration
Pin Description
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCAP
A12
A7
VCCX
W
HSB
A8
A9
A11
G
Signal Name Signal Description
A0 - A12
DQ0 - DQ7
Address Inputs
Data In/Out
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Chip Enable
E
PDIP
SOP
Output Enable
Write Enable
G
W
A10
E
9
VCCX
VSS
VCAP
Power Supply Voltage
Ground
Capacitor
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
Hardware Controlled Store/Busy
HSB
Top View
1
April 7, 2005