U632H16
PowerStore 2K x 8 nvSRAM
Features
S High-performance CMOS non-
volatile static RAM 2048 x 8 bits
S 25, 35 and 45 ns Access Times
S 12, 20 and 25 ns Output Enable
Access Times
S Packages: PDIP28 (300 mil)
automatically on power up. The
U632H16 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
SOP28 (300 mil)
Description
S ICC = 15 mA at 200 ns Cycle
Time
The U632H16 has two separate STORE cycles also may be initia-
modes of operation: SRAM mode ted under user control via a soft-
and nonvolatile mode. In SRAM ware sequence or via a single pin
mode, the memory operates as an (HSB).
S Automatic STORE to EEPROM
on Power Down using external
capacitor
ordinary static RAM. In nonvolatile Once a STORE cycle is initiated,
operation, data is transferred in further input or output are disabled
parallel from SRAM to EEPROM or until the cycle is completed.
from EEPROM to SRAM. In this Because a sequence of addresses
mode SRAM functions are disab- is used for STORE initiation, it is
S Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
S Automatic STORE Timing
S 106 STORE cycles to EEPROM
S 100 years data retention in
EEPROM
led.
important that no other read or
The U632H16 is a fast static RAM write accesses intervene in the
(25, 35, 45 ns), with a nonvolatile sequence or the sequence will be
S Automatic RECALL on Power Up electrically
erasable
PROM aborted.
S Software RECALL Initiation
(RECALL Cycle Time < 20 µs)
S Unlimited RECALL cycles from
EEPROM
(EEPROM) element incorporated RECALL cycles may also be initia-
in each static memory cell. The ted by a software sequence.
SRAM can be read and written an Internally, RECALL is a two step
unlimited number of times, while procedure. First, the SRAM data is
independent nonvolatile data resi- cleared and second, the nonvola-
des in EEPROM. Data transfers tile information is transferred into
from the SRAM to the EEPROM the SRAM cells.
S Single 5 V ± 10 % Operation
S Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
(the STORE operation) take place The RECALL operation in no way
automatically upon power down alters the data in the EEPROM
using charge stored in an external cells. The nonvolatile data can be
100 µF capacitor. Transfers from recalled an unlimited number of
the EEPROM to the SRAM (the times.
S QS 9000 Quality Standard
S ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
S RoHS compliance and Pb- free
RECALL operation) take place
Pin Description
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
VCAP
n.c.
A7
VCCX
W
HSB
A8
A9
n.c.
G
Signal Name Signal Description
A0 - A10
DQ0 - DQ7
Address Inputs
Data In/Out
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
Chip Enable
E
PDIP
SOP
Output Enable
Write Enable
G
W
A10
E
VCCX
VSS
VCAP
Power Supply Voltage
Ground
Capacitor
9
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
Hardware Controlled Store/Busy
HSB
16
15
Top View
1
April 7, 2005
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