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U631H256SM35 PDF预览

U631H256SM35

更新时间: 2024-09-17 15:55:47
品牌 Logo 应用领域
SIMTEK 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 196K
描述
Non-Volatile SRAM, 32KX8, 35ns, CMOS, PDSO28, 0.330 INCH, SOP1-28

U631H256SM35 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP28,.5Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.2最长访问时间:35 ns
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:18.1 mm内存密度:262144 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
功能数量:1端子数量:28
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:32KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP28,.5封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
认证状态:Not Qualified座面最大高度:2.54 mm
最大待机电流:0.002 A子类别:SRAMs
最大压摆率:0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.75 mmBase Number Matches:1

U631H256SM35 数据手册

 浏览型号U631H256SM35的Datasheet PDF文件第2页浏览型号U631H256SM35的Datasheet PDF文件第3页浏览型号U631H256SM35的Datasheet PDF文件第4页浏览型号U631H256SM35的Datasheet PDF文件第5页浏览型号U631H256SM35的Datasheet PDF文件第6页浏览型号U631H256SM35的Datasheet PDF文件第7页 
U631H256  
SoftStore 32K x 8 nvSRAM  
Features  
Description  
The U631H256 has two separate Once a STORE cycle is initiated,  
S High-performance CMOS non-  
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode further input or output are disabled  
S 25, 35 and 45 ns Access Times  
S 10, 15 and 20 ns Output Enable  
Access Times  
and nonvolatile mode. In SRAM until the cycle is completed.  
mode, the memory operates as an Because a sequence of addresses  
ordinary static RAM. In nonvolatile is used for STORE initiation, it is  
operation, data is transferred in important that no other read or  
parallel from SRAM to EEPROM or write accesses intervene in the  
from EEPROM to SRAM. In this sequence or the sequence will be  
mode SRAM functions are disab- aborted.  
S Software STORE Initiation  
S Automatic STORE Timing  
S 106 STORE cycles to EEPROM  
S 100 years data retention in  
EEPROM  
led.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
S Automatic RECALL on Power Up The U631H256 is a fast static RAM  
S Software RECALL Initiation  
S Unlimited RECALL cycles from  
EEPROM  
(25, 35, 45 ns), with a nonvolatile cleared and second, the nonvola-  
electrically  
erasable  
PROM tile information is transferred into  
(EEPROM) element incorporated the SRAM cells.  
in each static memory cell. The The RECALL operation in no way  
SRAM can be read and written an alters the data in the EEPROM  
unlimited number of times, while cells. The nonvolatile data can be  
independent nonvolatile data resi- recalled an unlimited number of  
des in EEPROM. Data transfers times.  
S Unlimited Read and Write to  
SRAM  
S Single 5 V ± 10 % Operation  
S Operating temperature ranges:  
0 to 70 °C  
-40 to 85 °C  
from the SRAM to the EEPROM The U631H256 is pin compatible  
(the STORE operation), or from the with standard SRAMs.  
EEPROM to the SRAM (the  
-55 to 125 °C (only 35 ns)  
S QS 9000 Quality Standard  
S ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
S RoHS compliance and Pb- free  
S Packages:  
RECALL operation) are initiated  
through software sequences.  
The U631H256 combines the high  
performance and ease of use of a  
PDIP28 (600 mil, only C/K-Type)  
SOP28 (330 mil)  
fast SRAM with nonvolatile data  
integrity.  
Pin Description  
Pin Configuration  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
W
A13  
A8  
A9  
A11  
G
Signal Name Signal Description  
A0 - A14  
DQ0 - DQ7  
Address Inputs  
Data In/Out  
PDIP  
SOP  
Chip Enable  
E
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
A10  
E
G
W
VCC  
VSS  
9
A0  
10  
11  
12  
13  
14  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ0  
DQ1  
DQ2  
VSS  
Top View  
1
April 7, 2005  

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