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U631H256D1C45G1 PDF预览

U631H256D1C45G1

更新时间: 2024-11-08 07:06:39
品牌 Logo 应用领域
SIMTEK 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 196K
描述
Non-Volatile SRAM, 32KX8, 45ns, CMOS, PDIP28, 0.600 INCH, GREEN, PLASTIC, DIP-28

U631H256D1C45G1 数据手册

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U631H256  
SoftStore 32K x 8 nvSRAM  
Features  
Description  
The U631H256 has two separate Once a STORE cycle is initiated,  
S High-performance CMOS non-  
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode further input or output are disabled  
S 25, 35 and 45 ns Access Times  
S 10, 15 and 20 ns Output Enable  
Access Times  
and nonvolatile mode. In SRAM until the cycle is completed.  
mode, the memory operates as an Because a sequence of addresses  
ordinary static RAM. In nonvolatile is used for STORE initiation, it is  
operation, data is transferred in important that no other read or  
parallel from SRAM to EEPROM or write accesses intervene in the  
from EEPROM to SRAM. In this sequence or the sequence will be  
mode SRAM functions are disab- aborted.  
S Software STORE Initiation  
S Automatic STORE Timing  
S 106 STORE cycles to EEPROM  
S 100 years data retention in  
EEPROM  
led.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
S Automatic RECALL on Power Up The U631H256 is a fast static RAM  
S Software RECALL Initiation  
S Unlimited RECALL cycles from  
EEPROM  
(25, 35, 45 ns), with a nonvolatile cleared and second, the nonvola-  
electrically  
erasable  
PROM tile information is transferred into  
(EEPROM) element incorporated the SRAM cells.  
in each static memory cell. The The RECALL operation in no way  
SRAM can be read and written an alters the data in the EEPROM  
unlimited number of times, while cells. The nonvolatile data can be  
independent nonvolatile data resi- recalled an unlimited number of  
des in EEPROM. Data transfers times.  
S Unlimited Read and Write to  
SRAM  
S Single 5 V ± 10 % Operation  
S Operating temperature ranges:  
0 to 70 °C  
-40 to 85 °C  
from the SRAM to the EEPROM The U631H256 is pin compatible  
(the STORE operation), or from the with standard SRAMs.  
EEPROM to the SRAM (the  
-55 to 125 °C (only 35 ns)  
S QS 9000 Quality Standard  
S ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
S RoHS compliance and Pb- free  
S Packages:  
RECALL operation) are initiated  
through software sequences.  
The U631H256 combines the high  
performance and ease of use of a  
PDIP28 (600 mil, only C/K-Type)  
SOP28 (330 mil)  
fast SRAM with nonvolatile data  
integrity.  
Pin Description  
Pin Configuration  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
W
A13  
A8  
A9  
A11  
G
Signal Name Signal Description  
A0 - A14  
DQ0 - DQ7  
Address Inputs  
Data In/Out  
PDIP  
SOP  
Chip Enable  
E
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
A10  
E
G
W
VCC  
VSS  
9
A0  
10  
11  
12  
13  
14  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ0  
DQ1  
DQ2  
VSS  
Top View  
1
April 7, 2005  

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