U630H16
HardStore 2K x 8 nvSRAM
Features
Description
! High-performance CMOS nonvo-
latile static RAM 2048 x 8 bits
! 25, 35 and 45 ns Access Times
! 12, 20 and 25 ns Output Enable
Access Times
The U630H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
! Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
! Automatic STORE Timing
! 105 STORE cycles to EEPROM
! 10 years data retention in
EEPROM
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
! Automatic RECALL on Power Up The U630H16 is a fast static RAM
! Hardware RECALL Initiation
(RECALL Cycle Time < 20 µs)
! Unlimited RECALL cycles from
EEPROM
(25, 35, 45 ns), with a nonvolatile
electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
! Unlimited Read and Write to
SRAM
! Single 5 V ± 10 % Operation
! Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
-40 to 125 °C (only 35 ns)
! QS 9000 Quality Standard
! ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code Num-
bers)
! Packages:SOP28 (300 mil),
PDIP28 (300/600 mil,
Once a STORE cycle is initiated,
only C/K-Type)
Pin Configuration
Pin Description
1
2
3
4
5
6
7
8
NE
n.c.
A7
A6
A5
A4
A3
A2
A1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
n.c.
A8
A9
n.c.
G
Signal Name Signal Description
A0 - A10
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable
E
PDIP
SOP
Output Enable
Write Enable
G
W
A10
E
9
NE
VCC
VSS
Nonvolatile Enable
Power Supply Voltage
Ground
10
11
12
13
14
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
VSS
Top View
1
April 20, 2004