U62H1708
Automotive Fast 128K x 8 SRAM
Features
Description
The U62H1708 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
! 131072 x 8 bit static CMOS RAM
! 35 and 55 ns Access Time
! Common data inputs and
data outputs
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
- Read
- Write
- Standby
! Three-state outputs
! Typ. operating supply current
35 ns: 45mA
- Data Retention
The memory array is based on a
6-Transistor cell.
55 ns: 30mA
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H) each address change
leads to a new Read cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
! Standby current <200µA at 125°C
! TTL/CMOS-compatible
! Power supply voltage 5 V
! Operating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity >100 mA
! Package: SOP32 (450 mil)
TSOP I 32
Data retention is guaranteed down
to 2 V. With the exception of E1
and E2, all inputs consist of NOR
gates, so that no pull-up/pull-down
resistors are required.
sTSOP I 32
Pin Configuration
Pin Description
1
32
31
30
29
28
27
26
25
24
23
22
21
20
VCC
A15
E2
1
32
31
30
29
28
27
26
25
24
23
22
21
20
G
n.c.
A16
A14
A12
A7
A11
A9
2
2
A10
E1
3
A8
3
4
A13
W
4
W
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name Signal Description
5
A13
A8
5
A0 - A16
DQ0 - DQ7
Address Inputs
Data In/Out
A6
6
E2
6
A5
7
A9
A15
VCC
n.c.
A16
A14
A12
A7
7
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
E1
E2
G
TSOP
SOP
A4
8
A11
8
sTSOP
A3
9
9
G
A10
VSS
DQ2
A2
10
11
12
13
14
15
16
10
11
12
13
14
15
16
W
A1
E1
DQ7
DQ1
DQ0
VCC
VSS
n.c.
A0
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
A0
A1
A2
A3
not connected
19
18
17
A6
19
18
17
A5
A4
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1
April 21, 2004