Datasheet > U6264BDC07G1

U6264BDC07G1

更新时间： 2024-09-13 07:05:23

品牌	Logo	应用领域
ZMD		静态存储器
页数	文件大小	规格书
9页	163K
描述
STANDARD 5K X 8 SRAM

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中文翻译

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数据手册

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U6264BDC07G1 数据手册

U6264B

Standard 8K x 8 SRAM

Features

Description

! 8192 x 8 bit static CMOS RAM

! 70 ns Access Times

! Common data inputs and

outputs

The U6264B is a static RAM manu-

factured using a CMOS process

technology with the following ope-

rating modes:

address, data input and control

signals W or G, the operating cur-

rent (at I_O= 0 mA) drops to the

value of the operating current in the

Standby mode. The Read cycle is

finished by the falling edge of E2 or

W, or by the rising edge of E1,

respectively.

! Three-state outputs

! Typ. operating supply current

70 ns: 10 mA

- Read

- Write

- Standby

- Data Retention

The memory array is based on a

6-transistor cell.

! Standby current:

< 2 µA at T ≤ 70 °C

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active. In a

Read cycle, the data outputs are

activated by the falling edge of G,

afterwards the data word read will

be available at the outputs DQ0 -

DQ7. After the address change, the

data outputs go High-Z until the

new read information is available.

The data outputs have no preferred

state. If the memory is driven by

CMOS levels in the active state,

and if there is no change of the

Data retention is guaranteed down

to 2 V. With the exception of E2, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required. This gate circuit

allows to achieve low power

standby requirements by activation

with TTL-levels too.

! Data retention current at 2 V:

< 1 µA at T ≤ 70 °C

! TTL/CMOS-compatible

! Automatic reduction of power

dissipation in long Read or Write

cycles

! Power supply voltage 5 V

! Operating temperature ranges:

0 to 70 °C

If the circuit is inactivated by

E2 = L, the standby current (TTL)

drops to 150 µA typ.

-40 to 85 °C

-40 to 125 °C

! QS 9000 Quality Standard

! ESD protection > 2000 V

(MIL STD 883C M3015.7)

! Latch-up immunity > 100 mA

! Packages: PDIP28 (600 mil)

SOP28 (330 mil)

Pin Configuration

Pin Description

Signal Name Signal Description

n.c.

A12

VCC

A0 - A12

Address Inputs

Data In/Out

W (WE)

E2 (CE2)

A11

G (OE)

A10

E1 (CE1)

DQ7

DQ6

DQ5

DQ0 - DQ7

Chip Enable 1

Chip Enable 2

Output Enable

Write Enable

Power Supply Voltage

Ground

PDIP

SOP

DQ0

DQ1

DQ2

VSS

VCC

VSS

DQ4

DQ3

not connected

n.c.

Top View

April 20, 2004

12 3 4 5 6 7...9

中文翻译

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与U6264BDC07G1相关器件

型号	品牌	获取价格	描述	数据表
U6264BDC07LL	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BDC07LLG1	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BDK07	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BDK07G1	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BDK07LL	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BDK07LL	CYPRESS	获取价格	8KX8 STANDARD SRAM, 70ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28
U6264BDK07LLG1	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BS2A07	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BS2A07G1	ZMD	获取价格	STANDARD 5K X 8 SRAM
U6264BS2A07G1	CYPRESS	获取价格	Standard SRAM, 8KX8, 70ns, CMOS, PDSO28, 0.330 INCH, LEAD FREE, SOP2-28

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