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U6264AS1C07LLG1 PDF预览

U6264AS1C07LLG1

更新时间: 2024-02-25 16:07:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
9页 87K
描述
8KX8 STANDARD SRAM, 70ns, PDSO28, 0.330 INCH, SOP-28

U6264AS1C07LLG1 技术参数

是否无铅:不含铅生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.55Is Samacsys:N
最长访问时间:70 nsJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:18.1 mm
内存密度:65536 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:2.54 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.75 mmBase Number Matches:1

U6264AS1C07LLG1 数据手册

 浏览型号U6264AS1C07LLG1的Datasheet PDF文件第2页浏览型号U6264AS1C07LLG1的Datasheet PDF文件第3页浏览型号U6264AS1C07LLG1的Datasheet PDF文件第4页浏览型号U6264AS1C07LLG1的Datasheet PDF文件第5页浏览型号U6264AS1C07LLG1的Datasheet PDF文件第6页浏览型号U6264AS1C07LLG1的Datasheet PDF文件第7页 
U6264A  
Standard 8K x 8 SRAM  
Features  
F 8192 x 8 bit static CMOS RAM  
F 70 and 100 ns Access Times  
F Common data inputs and  
outputs  
F Three-state outputs  
F Typ. operating supply current  
70 ns: 45 mA  
100 ns: 37 mA  
F Data retention current  
at 3 V: < 10 µA (standard)  
F Standby current standard < 30 µA factured using a CMOS process  
F Standby current low power  
(L) < 10 µA  
F Standby current very low power  
(LL) < 1 µA  
F Standby current for LL-version  
at 25 °C and 5 V: typ. 50 nA  
F TTL/CMOS-compatible  
F ESD protection > 2000 V  
(MIL STD 883C M3015.7)  
F Latch-up immunity > 100 mA  
F Packages: PDIP28 (600 mil)  
SOP28 (300 mil)  
G, afterwards the data word read  
will be available at the outputs  
DQ0 - DQ7. After the address  
change, the data outputs go High-Z  
until the new read information is  
available. The data outputs have  
no preferred state. If the memory is  
driven by CMOS levels in the  
active state, and if there is no  
change of the address, data input  
and control signals W or G, the  
operating current (at IO = 0 mA)  
drops to the value of the operating  
current in the Standby mode. The  
Read cycle is finished by the falling  
edge of E2 or W, or by the rising  
edge of E1, respectively.  
Data retention is guaranteed down  
to 2 V. With the exception of E2, all  
inputs consist of NOR gates, so  
that no pull-up/pull-down resistors  
are required. This gate circuit  
allows to achieve low power  
standby requirements by activation  
with TTL-levels too.  
SOP28 (330 mil)  
Description  
The U6264A is a static RAM manu-  
technology with the following ope-  
rating modes:  
- Read  
- Write  
- Standby  
- Data Retention  
The memory array is based on a  
6-transistor cell.  
The circuit is activated by the rising  
F Automatic reduction of power dis- edge of E2 (at E1 = L), or the falling  
sipation in long Read or Write  
cycles  
F Power supply voltage 5 V  
F Operating temperature ranges:  
0 to 70 °C  
-25 to 85 °C  
-40 to 85 °C  
F Quality assessment according to  
CECC 90000, CECC 90100 and  
CECC 90111  
edge of E1 (at E2 = H). The  
address and control inputs open  
simultaneously. According to the  
information of W and G, the data  
inputs, or outputs, are active.  
During the active state (E1 = L and  
E2 = H), each address change  
leads to a new Read or Write cycle.  
In a Read cycle, the data outputs  
are activated by the falling edge of  
If the circuit is inactivated by  
E2 = L, the standby current (TTL)  
drops to 150 µA typ.  
Pin Configuration  
Pin Description  
n.c.  
A12  
A7  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
1
VCC  
2
W (WE)  
E2 (CE2)  
A8  
Signal Name Signal Description  
3
A0 - A12  
Address Inputs  
Data In/Out  
A6  
4
DQ0 - DQ7  
A5  
5
A9  
A4  
6
Chip Enable 1  
Chip Enable 2  
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
A11  
E1  
A3  
7
G (OE)  
A10  
PDIP  
SOP  
E2  
A2  
8
G
A1  
9
E1 (CE1)  
DQ7  
W
A0  
10  
11  
12  
13  
14  
VCC  
VSS  
DQ0  
DQ1  
DQ2  
VSS  
DQ6  
DQ5  
not connected  
n.c.  
DQ4  
DQ3  
Top View  
November 01, 2001  
1

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