Datasheet > U6264ADK07L

U6264ADK07L

更新时间： 2024-01-23 03:57:19

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器光电二极管
页数	文件大小	规格书
9页	179K
描述
STANDARD 8K X 8 SRAM

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中文翻译

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数据手册

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U6264ADK07L 数据手册

U6264A

Standard 8K x 8 SRAM

ESD protection > 2000 V

(MIL STD 883C M3015.7)

Latch-up immunity > 100 mA

Packages: PDIP28 (600 mil)

SOP28 (300 mil)

DQ0 - DQ7. After the address

Features

change, the data outputs go High-Z

until the new read information is

available. The data outputs have no

preferred state. If the memory is

driven by CMOS levels in the active

state, and if there is no change of

the address, data input and control

signals W or G, the operating cur-

rent (at I_O= 0 mA) drops to the

value of the operating current in the

Standby mode. The Read cycle is

finished by the falling edge of E2 or

W, or by the rising edge of E1,

respectively.

8192 x 8 bit static CMOS RAM

70 and 100 ns Access Times

Common data inputs and

outputs

Three-state outputs

Typ. operating supply current

70 ns: 45 mA

SOP28 (330 mil)

Description

The U6264A is a static RAM manu-

factured using a CMOS process

technology with the following ope-

rating modes:

100 ns: 37 mA

Data retention current

at 3 V: < 10 µA (standard)

Standby current standard < 30 µA

Standby current low power

(L) < 10 µA

- Read

- Write

- Standby

- Data Retention

The memory array is based on a

6-transistor cell.

Data retention is guaranteed down

to 2 V. With the exception of E2, all

Standby current very low power

(LL) < 1 µA

The circuit is activated by the rising inputs consist of NOR gates, so that

edge of E2 (at E1 = L), or the falling no pull-up/pull-down resistors are

Standby current for LL-version

at 25 °C and 5 V: typ. 50 nA

TTL/CMOS-compatible

Automatic reduction of power

dissipation in long Read or Write

cycles

edge of E1 (at E2

= H). The required. This gate circuit allows to

address and control inputs open achieve low power standby require-

simultaneously. According to the ments by activation with TTL-levels

information of W and G, the data too.

inputs, or outputs, are active. If the circuit is inactivated by

During the active state (E1 = L and E2 = L, the standby current (TTL)

E2 = H), each address change drops to 150 µA typ.

leads to a new Read or Write cycle.

Power supply voltage 5 V

Operating temperature ranges:

0 to 70 °C

-25 to 85 °C

In a Read cycle, the data outputs

-40 to 85 °C

are activated by the falling edge of

G, afterwards the data word read

will be available at the outputs

Quality assessment according to

CECC 90000, CECC 90100 and

CECC 90111

Pin Description

Pin Configuration

n.c.

A12

VCC

W (WE)

E2 (CE2)

Signal Name Signal Description

A0 - A12

Address Inputs

Data In/Out

A11

DQ0 - DQ7

G (OE)

A10

PDIP

SOP

Chip Enable 1

Chip Enable 2

Output Enable

Write Enable

Power Supply Voltage

Ground

E1 (CE1)

DQ7

DQ0

DQ1

DQ2

VSS

DQ6

VCC

VSS

DQ5

DQ4

not connected

n.c.

DQ3

Top View

December 12, 1997

12 3 4 5 6 7...9

中文翻译

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与U6264ADK07L相关器件

型号	品牌	获取价格	描述	数据表
U6264ADK07LL	ETC	获取价格	STANDARD 8K X 8 SRAM
U6264ADK10	ETC	获取价格	STANDARD 8K X 8 SRAM
U6264ADK10L	ETC	获取价格	STANDARD 8K X 8 SRAM
U6264ADK10LL	ETC	获取价格	STANDARD 8K X 8 SRAM
U6264AS1A07	ZMD	获取价格	Automotive 8K x 8 SRAM
U6264AS1C07	ETC	获取价格	STANDARD 8K X 8 SRAM
U6264AS1C07L	ETC	获取价格	STANDARD 8K X 8 SRAM
U6264AS1C07LG1	CYPRESS	获取价格	8KX8 STANDARD SRAM, 70ns, PDSO28, 0.330 INCH, SOP-28
U6264AS1C07LL	ETC	获取价格	STANDARD 8K X 8 SRAM
U6264AS1C07LLG1	CYPRESS	获取价格	8KX8 STANDARD SRAM, 70ns, PDSO28, 0.330 INCH, SOP-28

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