Datasheet > U62256ADA10

U62256ADA10

更新时间： 2024-11-05 05:53:15

品牌	Logo	应用领域
ZMD		静态存储器
页数	文件大小	规格书
10页	164K
描述
STANDARD 32K X 8 SRAM

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数据手册

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U62256ADA10 数据手册

U62256A

Standard 32K x 8 SRAM

Description

Features

falling edge of W, or by the rising

edge of E, respectively.

! 32768x8 bit static CMOS RAM

! Access times 70 ns, 100 ns

! Common data inputs and

data outputs

The U62256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

! Three-state outputs

- Read

- Write

- Standby

! Typ. operating supply current

70 ns: 50 mA

- Data Retention

The memory array is based on a

6-transistor cell.

100 ns: 40 mA

! TTL/CMOS-compatible

! Automatical reduction of power

dissipation in long Read Cycles

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word read will be available at

the outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

read is available. The data outputs

have not preferred state.

! Power supply voltage 5 V 10 %

! Operating temperature ranges

0 to 70 °C

-40 to 85 °C

-40 to 125 °C

! QS 9000 Quality Standard

! ESD protection > 2000 V

(MIL STD 883C M3015.7)

! Latch-up immunity >100 mA

! Packages: PDIP28 (600 mil)

SOP28 (330 mil)

The Read cycle is finished by the

Pin Configuration

Pin Description

VCC

A14

A12

A13

A11

Signal Name Signal Description

A0 - A14

DQ0 - DQ7

Address Inputs

Data In/Out

A10

Chip Enable

PDIP

SOP

Output Enable

Write Enable

Power Supply Voltage

Ground

VCC

VSS

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

VSS

Top View

April 20, 2004

12 3 4 5 6 7...10

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