Datasheet > U62256

U62256

更新时间： 2024-11-04 22:18:15

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
9页	80K
描述
STANDARD 32K X 8 SRAM

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U62256 数据手册

U62256

Standard 32K x 8 SRAM

Description

Features

falling edge of W, or by the rising

edge of E, respectively.

F 32768x8 bit static CMOS RAM

F Access times 70 ns, 100 ns

F Common data inputs and

data outputs

F Three-state outputs

F Typ. operating supply current

70 ns: 50 mA

The U62256 is a static RAM manu-

factured using a CMOS process

technology with the following ope-

rating modes:

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

- Read

- Write

- Standby

- Data Retention

The memory array is based on a

MIXMOS cell.

100 ns: 40 mA

F TTL/CMOS-compatible

F Automatical reduction of power

dissipation in long Read Cycles

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word read will be available at

the outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

read is available. The data outputs

have not preferred state.

F Power supply voltage 5 V 10 %

F Operating temperature ranges

0 to 70 °C

-40 to 85 °C

F CECC 90000 Quality Standard

F ESD protection > 2000 V

(MIL STD 883C M3015.7)

F Latch-up immunity >100 mA

F Package: SOP28 (330 mil)

The Read cycle is finished by the

Pin Configuration

Pin Description

VCC

A14

A12

A13

Signal Name Signal Description

A0 - A14

Address Inputs

Data In/Out

A11

DQ0 - DQ7

Chip Enable

SOP

A10

Output Enable

Write Enable

Power Supply Voltage

Ground

DQ7

VCC

VSS

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

VSS

Top View

November 01, 2001

12 3 4 5 6 7...9

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