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U4076B-FL PDF预览

U4076B-FL

更新时间: 2024-11-27 22:18:19
品牌 Logo 应用领域
TEMIC 电信集成电路电信电路电话电路光电二极管异步传输模式ATM
页数 文件大小 规格书
6页 92K
描述
Three-Tone Ringer for Telephone Sets

U4076B-FL 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.67Is Samacsys:N
JESD-30 代码:R-PDSO-G16功能数量:1
端子数量:16最高工作温度:60 °C
最低工作温度:-25 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not Qualified表面贴装:YES
电信集成电路类型:TELEPHONE RINGER CIRCUIT温度等级:OTHER
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

U4076B-FL 数据手册

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U4076B  
Three-Tone Ringer for Telephone Sets  
Description  
The three-tone ringing integrated circuit U4076B, in There is also a possibility of operating the IC with the dc  
conjunction with a piezo transducer or loudspeaker supply voltage, being developed for large operating  
replaces the normal electromechanical telephone bell. It range. The integrated circuit is overload protected.  
is operated with the ringing current from the exchange.  
Features  
Three-tone ringing sequence with 800 Hz, 1067 Hz  
and 1333 Hz  
Clock oscillator with ceramic resonator or LC series  
cct possible  
Sequence frequency adjustable between 2.5 Hz and  
25 Hz  
Input protective diode  
On-chip rectifier bridge  
Adjustable volume  
Push-pull output stage  
Protection circuit against ringing in a parallel circuit  
Piezo transducer or loudspeaker connection  
Common input for frequency and call recognition  
Benefit  
Reduced pulse duration for electromagnetic  
transducers  
Suitable for German Post Office Specification,  
FTZ 121671 Pfl. 3, edition dated 24.03.82  
43 k  
4.7 nF  
22  
F
6
600 k  
Ground: output signal  
Open: output signal  
4
(5)  
(7)  
10 (11)  
8
(9)  
9
(10)  
(15) 13  
2.2 k  
F
7
a
(8)  
0.8  
Tone sequence  
oscillator  
12  
Supply  
~
~
b
(13)  
5
Divider  
32:1  
Tone signal  
generator  
Level  
(6)  
monitoring  
11  
(12)  
100 k  
log  
Reset  
a
96 ms  
127 ms  
Divider  
128:1  
Divider  
2:1  
Reset  
b
Frequency  
monitoring  
R
L
14  
Frequency  
(16)  
1
2 (2)  
3 (3)  
455 kHz  
Three  
state  
Divider  
32:1  
Divider  
14:1  
Clock signal  
generator  
(1)  
93 7792 e  
Figure 1. Block diagram and application circuit  
Case: DIP14 or SO16-L (Pin connections for SO 16-L case in bracket)  
TELEFUNKEN Semiconductors  
1 (6)  
Rev. A1, 15-May-96  
Preliminary Information  

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