ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ
ꢊꢋ ꢋꢋ ꢄ ꢌ ꢍ ꢃ ꢎ ꢁꢊ ꢏꢐꢑ ꢒꢓꢀ ꢔꢉꢂ ꢅꢋ ꢀ ꢓꢉꢕꢁ ꢔꢋꢊ ꢆꢋꢓꢖ ꢉ ꢓꢂ ꢊ ꢀꢋ ꢓ
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
D
Fully Supports Provisions of IEEE 1394−
D
Register Bits Give Software Control of
Contender Bit, Power Class bits, Link
Active Control Bit and P1394a Features
1995 Standard for High Performance Serial
†
Bus and the P1394a Supplement
D
D
D
Fully Interoperable With FireWire and
i.LINK Implementation of IEEE Std 1394
Fully Compliant With OpenHCI
Requirements
D
D
Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
Interface to Link Layer Controller Supports
Low Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation
Provides Six P1394a Fully Compliant Cable
Ports at 100/200/400 Megabits per Second
(Mbits/s)
D
D
D
Interoperable With Link-Layer Controllers
Using 3.3 V and 5 V Supplies
D
Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset,
Multispeed Concatenation, Arbitration
Acceleration, Fly-By Concatenation, Port
Disable/Suspend/Resume
Interoperable With Other Physical Layers
(PHYs) Using 3.3 V and 5 V Supplies
Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
D
D
Extended Resume Signaling for
Compatibility With Legacy DV Devices
D
D
D
D
D
D
Incoming Data Resynchronized to Local
Clock
Power-Down Features to Conserve Energy
in Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Terminal,
Link Interface Disable via LPS, and Inactive
Ports Powered-Down
Logic Performs System Initialization and
Arbitration Functions
Encode and Decode Functions Included for
Data-Strobe Bit Level Encoding
Separate Cable Bias (TPBIAS) for Each Port
Single 3.3-V Supply Operation
D
D
Ultralow-Power Sleep Mode
Node Power Class Information Signaling
for System Power Management
Low Cost High Performance 100-Pin TQFP
(PZP) Thermally Enhanced Package
D
Cable Power Presence Monitoring
D
Direct Drop-In Upgrade for TSB41LV06PZP
D
Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
description
The TSB41LV06A provides the digital and analog transceiver functions needed to implement a six-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV06A is designed to
interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12LV01A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
i.LINK is a trademark of Sony Corporation
FireWire is a trademark of Apple Computer, Incorporated.
ꢑ
ꢑ
ꢓ
ꢒ
ꢧ
ꢗ
ꢢ
ꢘ
ꢔ
ꢠ
ꢀ
ꢡ
ꢊ
ꢜ
ꢒ
ꢚ
ꢕ
ꢛ
ꢗ
ꢉ
ꢀ
ꢉ
ꢙ
ꢚ
ꢣ
ꢛ
ꢜ
ꢡ
ꢝ
ꢞ
ꢎ
ꢎ
ꢟ
ꢟ
ꢙ
ꢙ
ꢜ
ꢜ
ꢚ
ꢚ
ꢙ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢝ
ꢝ
ꢣ
ꢣ
ꢚ
ꢟ
ꢎ
ꢞ
ꢠ
ꢠ
ꢜ
ꢛ
ꢤ
ꢀꢣ
ꢢ
ꢥ
ꢠ
ꢦ
ꢙ
ꢡ
ꢎ
ꢠ
ꢟ
ꢙ
ꢟ
ꢜ
ꢝ
ꢚ
ꢢ
ꢧ
ꢎ
ꢚ
ꢟ
ꢟ
ꢣ
ꢠ
ꢨ
Copyright 2000, Texas Instruments Incorporated
ꢝ
ꢜ
ꢡ
ꢟ
ꢜ
ꢝ
ꢞ
ꢟ
ꢜ
ꢠ
ꢤ
ꢙ
ꢛ
ꢙ
ꢡ
ꢣ
ꢝ
ꢟ
ꢩ
ꢟ
ꢣ
ꢝ
ꢜ
ꢛ
ꢪ
ꢎ
ꢊ
ꢚ
ꢞ
ꢣ
ꢠ
ꢟ
ꢎ
ꢚ
ꢧ
ꢎ
ꢝ
ꢧ
ꢫ
ꢎ
ꢟ ꢣ ꢠ ꢟꢙ ꢚꢭ ꢜꢛ ꢎ ꢦꢦ ꢤꢎ ꢝ ꢎ ꢞ ꢣ ꢟ ꢣ ꢝ ꢠ ꢨ
ꢝ
ꢝ
ꢎ
ꢚ
ꢟ
ꢬ
ꢨ
ꢑ
ꢝ
ꢜ
ꢧ
ꢢ
ꢡ
ꢟ
ꢙ
ꢜ
ꢚ
ꢤ
ꢝ
ꢜ
ꢡ
ꢣ
ꢠ
ꢠꢙ
ꢚ
ꢭ
ꢧ
ꢜ
ꢣ
ꢠ
ꢚ
ꢜ
ꢟ
ꢚ
ꢣ
ꢡꢣ
ꢠ
ꢠ
ꢎ
ꢝ
ꢙ
ꢦ
ꢬ
ꢙ
ꢚ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265