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TSB14C01MPM PDF预览

TSB14C01MPM

更新时间: 2024-11-24 13:14:55
品牌 Logo 应用领域
德州仪器 - TI 局域网
页数 文件大小 规格书
31页 441K
描述
SPECIALTY TELECOM CIRCUIT, PQFP64, PLASTIC, TQFP-64

TSB14C01MPM 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-64针数:64
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
接口集成电路类型:LINE TRANSCEIVERJESD-30 代码:S-PQFP-G64
长度:10 mm功能数量:1
端子数量:64封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.6 mm表面贴装:YES
温度等级:MILITARY端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

TSB14C01MPM 数据手册

 浏览型号TSB14C01MPM的Datasheet PDF文件第2页浏览型号TSB14C01MPM的Datasheet PDF文件第3页浏览型号TSB14C01MPM的Datasheet PDF文件第4页浏览型号TSB14C01MPM的Datasheet PDF文件第5页浏览型号TSB14C01MPM的Datasheet PDF文件第6页浏览型号TSB14C01MPM的Datasheet PDF文件第7页 
TSB14C01  
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER  
SLLS231B – MARCH 1996 – REVISED MAY 1997  
Supports Provisions of IEEE 1394-1995  
Separate Transmitter and Receiver for  
Greater Flexibility  
(1394) Standard for High-Performance  
Serial Bus  
Data Interface to Link-Layer Controller  
(Link) Provided Through Two Parallel  
Signal Lines at 25/50 MHz  
Fully Interoperable With FireWire  
Implementation of 1394  
Provides A Backplane Environment That  
Supports 50 or 100 Megabits per Second  
(Mbits/s)  
100-MHz or 50-MHz Oscillator Provides  
Transmit, Receive-Data, and Link Clocks at  
25/50 MHz  
Logic Performs System Initialization and  
Arbitration Functions  
Single 5-V Supply Operation  
Packaged in a High-Performance 64-Pin  
TQFP (PM) Package for 0°C to 70°C  
Operation  
Encode and Decode Functions Included for  
Data-Strobe Bit-Level Encoding  
Incoming Data Resynchronized to Local  
Clock  
Packaged in a 68-Pin CFP (HV) Package for  
55°C to 125°C Operation  
description  
The TSB14C01 provides the transceiver functions needed to implement a single port node in a backplane-  
based 1394 network. The TSB14C01 provides two terminals for transmitting, two terminals for receiving, and  
a single terminal to externally control the drivers for data and strobe. The TSB14C01 is not designed to drive  
the backplane directly, this function must be provided externally. The TSB14C01 is designed to interface with  
a link-layer controller (link), such as the TSB12C01A.  
The TSB14C01 requires an external 98.304-MHz or 49.152-MHz reference oscillator input for S100/50  
operation. The reference signal is internally divided to provide the 49.152-MHz ±100-ppm system clock signals  
used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock  
signalissuppliedtotheassociatedlinkforsynchronizationofthetwochips, whenthisdeviceisintheS100mode  
of operation, OSC_SEL is asserted high. When the TSB14C01 is in the S50 mode of operation, the clock rate  
supplied to the link is 24.576 MHz.  
Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the  
TSB14C01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded,  
and then transmitted at 98.304-Mbits/s (in S100 mode) as the outbound data-strobe information stream. During  
transmission, the encoded data information is transmitted on TDATA, and the encoded strobe information is  
transmitted on TSTRB.  
During packet reception the encoded information is received on RDATA and strobe information on RSTRB. The  
received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The  
serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the  
associated link.  
The TSB14C01 is a 5-V device and provides CMOS-level outputs.  
AVAILABLE OPTIONS  
PACKAGES  
T
A
CERAMIC FLAT PACK  
(HV)  
THIN QUAD FLAT PACK  
(PM)  
0°C to 70°C  
TSB14C01PM  
55°C to 125°C  
TSB14C01MHV  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.  
FireWire is a trademark of Apple Computer, Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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