Main Features
• 8-bit Resolution
• 500 Msps (min) Sampling Rate
• Power Consumption: 3.8W Typ
• 500 mVpp Differential or Single-ended Analog Inputs
• Differential or Single-ended 50Ω ECL Compatible Clock Inputs
• ECL or LVDS/HSTL Output Compatibility
• ADC Gain Adjust
• Data Ready Output with Asynchronous Reset
• Gray or Binary Selectable Output Data; NRZ Output Mode
• Enhanced CBGA Package with Ceramic Lid
• Evaluation Board: TSEV8308500GL (Detailed Specification on Request)
• Demultiplexer TS81102G0: Companion Device Available
ADC 8-bit
500 Msps
Performance
• 1.3 GHz Full Power Input Bandwidth
• Band Flatness: 0.5 dB up to 500 MHz
• SINAD = 45 dB (7.2 Effective Bits), SFDR = 54 dBc
at FS = 500 Msps, FIN = 20 MHz
TS8308500
• SINAD = 43 dB (7.1 Effective Bits), SFDR = 53 dBc
at FS = 500 Msps, FIN = 250 MHz
• SINAD = 42 dB (7.0 Effective Bits), SFDR = 52 dBc
at FS = 500 Msps, FIN = 500 MHz (-3 dB FS)
• 2-tone IMD: TBD (199.5 MHz, 200.5 MHz) at 500 Msps
• DNL = ±0.3 LSB INL = ±0.7 LSB
• Low Bit Error Rate (10-13) at 500 Msps, Tj = 90°C
Applications
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Digital Sampling Oscilloscopes
Satellite Receiver
Electronic Countermeasures/Electronic Warfare
Direct RF Down-conversion
Screening
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Atmel Standard Screening Level
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Temperature Range:
–
–
0°C < Tc; Tj < +90°C
-40°C < Tc ; Tj < + 110°C
Description
The TS8308500 is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 500 Msps.
The TS8308500 is using an innovative architecture, including an on-chip Sample and
Hold (S/H), and is fabricated with an advanced high-speed bipolar process.
The on-chip S/H has a 1.3 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
Rev. 2193A–BDC–046/03
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