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TS68040MRB/C33A PDF预览

TS68040MRB/C33A

更新时间： 2024-09-16 21:58:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 外围集成电路微处理器时钟
页数 文件大小 规格书
49页 1606K
描述
Third- Generation 32-bit Microprocessor

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中文翻译

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TS68040MRB/C33A 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：PGA包装说明：PGA, PGA179,18X18
针数：179Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.31.00.01
风险等级：5.24地址总线宽度：32
位大小：32边界扫描：YES
最大时钟频率：33 MHz外部数据总线宽度：32
格式：FLOATING POINT集成缓存：YES
JESD-30 代码：S-CPGA-P179长度：47.244 mm
低功率模式：NO端子数量：179
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：PGA
封装等效代码：PGA179,18X18封装形状：SQUARE
封装形式：GRID ARRAY电源：5 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B
座面最大高度：3.275 mm速度：33 MHz
子类别：Microprocessors最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：HCMOS
温度等级：MILITARY端子形式：PIN/PEG
端子节距：2.54 mm端子位置：PERPENDICULAR
宽度：47.244 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR
Base Number Matches：1

TS68040MRB/C33A 数据手册

 浏览型号TS68040MRB/C33A的Datasheet PDF文件第2页浏览型号TS68040MRB/C33A的Datasheet PDF文件第3页浏览型号TS68040MRB/C33A的Datasheet PDF文件第4页浏览型号TS68040MRB/C33A的Datasheet PDF文件第5页浏览型号TS68040MRB/C33A的Datasheet PDF文件第6页浏览型号TS68040MRB/C33A的Datasheet PDF文件第7页 
Features  
• 26-42 MIPS Integer Performance  
• 3.5-5.6 MFLOPS Floating-Point-Performance  
• IEEE 754-Compatible FPU  
• Independent Instruction and Data MMUs  
• 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed  
Simultaneously  
• 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface  
• User-Object-Code Compatibility with All Earlier TS68000 Microprocessors  
• Multimaster/Multiprocessor Support via Bus Snooping  
• Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize  
Throughput  
Third-  
Generation  
32-bit  
• 4G bytes Direct Addressing Range  
• Software Support Including Optimizing C Compiler and UNIX® System V Port  
• IEEE P 1149-1 Test Mode (JTAG)  
• f = 25 MHz, 33 MHz; VCC = 5V ± 5%; PD = 7W  
• The Use of the TS88915T Clock Driver is Suggested  
Microprocessor  
Description  
The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-  
bit microprocessors. The TS68040 is a virtual memory microprocessor employing  
multiple, concurrent execution units and a highly integrated architecture to provide  
very high performance in a monolithic HCMOS device. On a single chip, the TS68040  
integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit  
(FPU), and fully independent instruction and data demand-paged memory manage-  
ment units (MMUs), including 4K bytes independent instruction and data caches. A  
high degree of instruction execution parallelism is achieved through the use of multi-  
ple independent execution pipelines, multiple internal buses, and a full internal  
Harvard architecture, including separate physical caches for both instruction and data  
accesses. The TS68040 also directly supports cache coherency in multimaster appli-  
cations with dedicated on-chip bus snooping logic.  
TS68040  
The TS68040 is user-object-code compatible with previous members of the TS68000  
Family and is specifically optimized to reduce the execution time of compiler-gener-  
ated code. The 68040 HCMOS technology, provides an ideal balance between speed,  
power, and physical device size.  
Figure 1 is a simplified block diagram of the TS68040. Instruction execution is pipe-  
lined in both the integer unit and FPU. Independent data and instruction MMUs control  
the main caches and the address translation caches (ATCs). The ATCs speed up log-  
ical-to-physical address translations by storing recently used translations. The bus  
snooper circuit ensures cache coherency in multimaster and multiprocessing  
applications.  
Screening  
•
•
•
MIL-STD-883  
DESC. Drawing 5962-93143  
Atmel Standards  
Rev. 2116A–HIREL–09/02  
1234567...49

中文翻译

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