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TS3A5017DG4 PDF预览

TS3A5017DG4

更新时间: 2024-11-26 06:02:47
品牌 Logo 应用领域
德州仪器 - TI 解复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
30页 1127K
描述
DUAL SP4T ANALOG SWITCH 3.3-V/2.5-V DUAL 4:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

TS3A5017DG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, MS-012AC, SOIC-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.64Is Samacsys:N
模拟集成电路 - 其他类型:SINGLE-ENDED MULTIPLEXERJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
湿度敏感等级:1信道数量:4
功能数量:2端子数量:16
标称断态隔离度:48 dB通态电阻匹配规范:1 Ω
最大通态电阻 (Ron):22 Ω最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.75 mm
最大信号电流:0.1 A子类别:Multiplexer or Switches
最大供电电流 (Isup):0.01 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES最长断开时间:6 ns
最长接通时间:10 ns切换:BREAK-BEFORE-MAKE
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

TS3A5017DG4 数据手册

 浏览型号TS3A5017DG4的Datasheet PDF文件第2页浏览型号TS3A5017DG4的Datasheet PDF文件第3页浏览型号TS3A5017DG4的Datasheet PDF文件第4页浏览型号TS3A5017DG4的Datasheet PDF文件第5页浏览型号TS3A5017DG4的Datasheet PDF文件第6页浏览型号TS3A5017DG4的Datasheet PDF文件第7页 
TS3A5017  
www.ti.com .......................................................................................................................................... SCDS188DJANUARY 2005REVISED DECEMBER 2008  
DUAL SP4T ANALOG SWITCH  
3.3-V/2.5-V DUAL 4:1 ANALOG MULTIPLEXER/DEMULTIPLEXER  
1
FEATURES  
DESCRIPTION  
Isolation in the Powered-Down Mode, V+ = 0  
Low ON-State Resistance  
The TS3A5017 is a dual single-pole quadruple-throw  
(4:1) analog switch that is designed to operate from  
2.3 V to 3.6 V. This device can handle both digital  
and analog signals, and signals up to V+ can be  
transmitted in either direction.  
Low Charge Injection  
Excellent ON-State Resistance Matching  
Low Total Harmonic Distortion (THD)  
2.3-V to 3.6-V Single-Supply Operation  
FUNCTION TABLE  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D TO S,  
EN  
IN2  
IN1  
S TO D  
D = S1  
D = S2  
D = S3  
D = S4  
OFF  
ESD Performance Tested Per JESD 22  
L
L
L
L
H
L
L
L
H
L
2000-V Human-Body Model  
(A114-B, Class II)  
H
H
X
H
X
1000-V Charged-Device Model (C101)  
APPLICATIONS  
Sample-and-Hold Circuits  
Battery-Powered Equipment  
Audio and Video Signal Routing  
Communication Circuits  
D, DBQ, DGV, OR PW PACKAGE  
(TOP VIEW)  
RGY PACKAGE  
(TOP VIEW)  
RSV PACKAGE  
(TOP VIEW)  
1EN  
1
V
+
Logic  
Control  
Logic  
Control  
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1EN  
IN2  
+
16  
16 15 14 13  
2EN  
IN1  
IN2  
2
3
4
5
6
7
15  
14 IN1  
2EN  
1S  
1S  
1S  
1
2
3
4
12  
11  
10  
9
IN1  
1S  
4
4
3
2
1S  
4
2S  
4
1S  
3
2S  
4
Exposed  
Center  
Pad  
1S  
3
2S  
2S  
2S  
2S  
13  
12  
11  
10  
4
3
2
1
2S  
3
1S  
2
2S  
3
1S  
2
1S  
2S  
2
1
1S  
2S  
2
1S  
1
1
5
6
7
8
2S  
1
1D  
1D  
8
9
GND  
2D  
GND  
2D  
If exposed center pad is used, it must be  
connected as a secondary ground  
or left electrically open.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2008, Texas Instruments Incorporated  

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