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TRF3761IRHAR PDF预览

TRF3761IRHAR

更新时间: 2024-11-28 08:37:11
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
18页 438K
描述
INTEGER-N PLL WITH INTEGRATED VCO

TRF3761IRHAR 技术参数

生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC40,.24SQ,20针数:40
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84其他特性:DUAL MODULUS PRESCALER : 8/9, 16/17, 32/33, 64/65
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERJESD-30 代码:S-PQCC-N40
长度:6 mm功能数量:1
端子数量:40最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC40,.24SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
电源:5 V认证状态:Not Qualified
座面最大高度:1 mm子类别:PLL or Frequency Synthesis Circuits
最大供电电流 (Isup):150 mA最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:6 mm
Base Number Matches:1

TRF3761IRHAR 数据手册

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TRF3761  
www.ti.com  
SLWS181OCTOBER 2005  
INTEGER-N PLL WITH INTEGRATED VCO  
FEATURES  
RHA PACKAGE  
(TOP VIEW)  
Fully Integrated VCO  
Low Phase Noise: -138 dBc/Hz (at 600 kHz,  
fVCO of 1.9 GHz )  
Low Noise Floor: -160dBc/Hz at 10 MHz Offset  
Integer-N PLL  
40 39 38 37 36 35 34 33 32 31  
1
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
PD_OUTBUF  
CHIP_EN  
CLOCK  
DATA  
GND  
Input Reference Frequency range: 10 104 MHz  
VCO Frequency Divided by 2-4 Output  
Output Buffer Enable Pin  
2
AVDD_BIAS  
RBIAS1  
3
4
GND  
Programmable Charge Pump Current  
Hardware and Software Power Down  
3-Wire Serial Interface  
5
STROBE  
GND  
VCTRL_IN  
AVDD_VCO  
AVDD_BUF  
AVDD_CAPARRAY  
GND  
6
7
GND  
8
DVDD1  
AVDD_PRES  
GND  
Single Supply: 4.5 V 5.25 V Operation  
Silicon Germanium Technology  
9
10  
AVDD  
11 12 13 14 15 16 17 18 19 20  
APPLICATIONS  
Wireless Infrastructure  
– WCDMA  
– CDMA  
– GSM  
DESCRIPTION  
TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized for wireless  
infrastructure applications. TRF3761 includes a low noise voltage controlled oscillator (VCO) and an integer-N  
PLL.  
TRF3761 integrates a divide-by-2 or 4 options for a more flexible output frequency range. It is controlled through  
a 3-wire serial interface programming (SPI) interface. It can be powered down when it is not used by the SPI or  
external pin.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCT PREVIEW information concerns products in the  
Copyright © 2005, Texas Instruments Incorporated  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  

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