Datasheet > TQ2059

TQ2059

更新时间： 2024-02-01 04:09:41

品牌	Logo	应用领域
TRIQUINT		时钟发生器
页数	文件大小	规格书
6页	199K
描述
High-Frequency Clock Generator

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中文翻译

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技术参数
数据手册

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TQ2059 技术参数

生命周期：	Active	包装说明：	QCCJ, LDCC28,.5SQ
Reach Compliance Code：	compliant	风险等级：	5.8
Is Samacsys：	N	JESD-30 代码：	S-PQCC-J28
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC28,.5SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
电源：	5 V	认证状态：	Not Qualified
子类别：	Clock Generators	最大压摆率：	120 mA
标称供电电压：	5 V	表面贴装：	YES
技术：	GAAS	温度等级：	COMMERCIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	Base Number Matches：	1

TQ2059 数据手册

S E M I C O N D U C T O R , I N C .

TQ2059

Figure 1. Pinout Diagram

High-Frequency

Clock Generator

VDD

Features

Phase

VCO

÷10

÷2

Detector

MUX

• Output frequency range:

200 MHz to 350 MHz

TEST1

TEST2

• One differential PECL output:

600 mV (min) swing

MUX

Control

• Common-mode voltage:

_DD–1.2 V (max),

_DD–1.6 V (min)

GND

• Period-to-period output jitter:

30 ps peak-to-peak (typ)

AVDD

120 ps peak-to-peak (max)

• Reference clock input:

20 MHz to 35 MHz TTL-level

crystal oscillator

TriQuint’s TQ2059 is a high-frequency clock generator. It utilizes a 20 MHz

to 35 MHz TTL input to generate a 200 MHz to 350 MHz PECL output. The

TQ2059 has a completely self-contained Phase-Locked Loop (PLL) running

at 400 MHz to 700 MHz. This stable PLL allows for a low period-to-period

output jitter of 120 ps (max), and enables tight duty-cycle control of 55%to

45% (worst case).

• Self-contained loop filter

• Optional 200-ohm pull-down

resistors for AC-coupled outputs

• +5 V power supply

• 28-pin J-lead surface-mount

package

The TQ2059 provides optional 200-ohm on-chip pull-down resistors which

are useful if the output is AC-coupled to the device being driven. In order

to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN),

and pin 23 (PDR1) should be connected to pin 22 (Q).

• Ideal for designs based on DEC

Alpha AXP^™processors

Various test modes on the chip simplify debug and testing of systems by

slowing the clock output or by bypassing the PLL.

For additional information and latest specifications, see our website: www.triquint.com

12 3 4 5 6

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