User's Guide
SLUU526–August 2011
Using the TPS51916EVM-746 Complete DDR2, DDR3,
DDR3L, and DDR4 Memory Power Solution Synchronous
Buck Controller, 2-A LDO, Buffered Reference
The TPS51916EVM-746 evaluation module (EVM) allows users to evaluate the performance of the
TPS51916 low-dropout (LDO) regulator. The TPS51916 provides a complete power supply for DDR2,
DDR3, DDR3L, and DDR4 memory system in the lowest total cost and minimum space. TPS51916
integrates a synchronous buck controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered,
low-noise reference (VTTREF).
Contents
1
Description ................................................................................................................... 3
1.1
1.2
Typical Applications ................................................................................................ 3
Features ............................................................................................................. 3
2
3
4
Electrical Performance Specifications .................................................................................... 3
Schematic .................................................................................................................... 5
Test Setup ................................................................................................................... 6
4.1
4.2
Test Equipment ..................................................................................................... 6
Recommended Test Setup ....................................................................................... 7
5
6
Configurations ............................................................................................................... 8
5.1
S3, S5 Enable Selection .......................................................................................... 8
Test Procedure .............................................................................................................. 8
6.1
6.2
6.3
Line/Load Regulation and Efficiency Measurement Procedure .............................................. 8
List of Test Points .................................................................................................. 8
Equipment Shutdown .............................................................................................. 9
7
Performance Data and Typical Characteristic Curves ................................................................. 9
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
DDR3 VDDQ Efficiency ........................................................................................... 9
DDR3 VDDQ Load Regulation .................................................................................. 10
DDR3 VDDQ Line Regulation .................................................................................. 10
DDR3 VTT Load Regulation .................................................................................... 11
DDR3 VTTREF Load Regulation ............................................................................... 11
DDR3 VTT Dropout Voltage .................................................................................... 12
DDR3 S5 Enable Turnon/Turnoff ............................................................................... 12
S5 Enable Turnon with 1-V Prebias at VDDQ ................................................................ 13
DDR3 S3 Enable Turnon/ Turnoff (S5 is ON) ................................................................ 13
7.10 DDR3 VDDQ Output Ripple ..................................................................................... 14
7.11 DDR3 VDDQ Switching Node .................................................................................. 14
7.12 DDR3 VDDQ Output Transient ................................................................................. 15
7.13 DDR3 VTT Transient With 1.5-A Sinking and Sourcing Current ........................................... 15
7.14 Thermal Image .................................................................................................... 16
7.15 DDR3 VDDQ Bode Plot ......................................................................................... 16
7.16 DDR3 VTT Bode Plot ............................................................................................ 17
EVM Assembly Drawing and PCB Layout ............................................................................. 17
Bill of Materials ............................................................................................................. 21
8
9
List of Figures
D-CAP2 is a trademark of Texas Instruments.
1
SLUU526–August 2011
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Using the TPS51916EVM-746 Complete DDR2, DDR3, DDR3L, and DDR4
Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered
Copyright © 2011, Texas Instruments Incorporated
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