Datasheet > TPK1031

TPK1031

更新时间： 2024-09-14 17:01:15

品牌	Logo	应用领域
思瑞浦 - 3PEAK		/
页数	文件大小	规格书
30页	1645K
描述
3-Channel Simple Power Sequencer with Adjustable Timing Control

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中文翻译

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数据手册

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TPK1031 数据手册

TPK1031

Quad Channel Jitter Cleaner Digital PLL

Temperature range: -40C to +85C

Features

•

Pb-free, RoHS-6 compliant

•

Quad DPLLs synchronize any physical layer clocks,

provides arbitrary frequency translation with jitter

cleaning

•

Complies with ITU-T G.8262 EEC-Option 1 and EEC-

Option 2 and G.8262.1

Ultra-low jitter of 80fs rms

•

Applications

Output frequency range:

Router/Switch

•

Differential: 8kHz to 1500MHz

–

PTN/OTN/PON/xDSL

•

Single-ended: 1Hz to 250MHz

–

Macro CellBBU/AAU

•

Format: LVDS/LVPECL/HCSL/CMOS with

programable signal amplitude

–

Samll Cell Radio

•

Input frequency range

•

Differential: 8kHz to 1000MHz

–

Single-ended: 1Hz to 250MHz

–

Format: LVDS/LVPECL/HCSL/CMOS

–

Programmable digital loop filter bandwidth: 1mHz to

4kHz

•

Flexible MUXs routes any input to any output

•

Automatic and manual holdover and reference

switchover, providing zero delay, hitless or phase

buildout operation

•

Programmable priority-based reference switching with

manual / automatic revertive / non-revertive modes

supported

•

Excellent phase buildout reference switching for 8kHz/

19.44MHz/25MHz/38.88MHz to minimize output phase

transient

•

Fast lock feature for low loop bandwidths

•

DCO mode: frequency resolution down to 1ppt (1e-12)

•

Reference monitor (reliable and fast validation),

programmable

•

Delay adjustment on reference, feedback path and

output channel

•

Delay adjustment on output (coarse / fine delay)

•

Phase Slop Limited Reference Switching (PSLRS)

•

In-circuit programmable with non-volatile memory

(NVM)

•

Core voltage

•

VDD: 1.8V+/-5%;

–

VDDA: 3.3V+/-5%

–

Independent output clock supply pins: 3.3V, 2.5V, or

1.8V +/-5%

•

Serial interface: SPI or I2C

•

Package: 64-QFN 9x9 mm

•

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中文翻译

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