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TPIC1321LDW PDF预览

TPIC1321LDW

更新时间: 2024-09-16 12:22:31
品牌 Logo 应用领域
德州仪器 - TI 栅极
页数 文件大小 规格书
14页 273K
描述
3-HALF H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY

TPIC1321LDW 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SMALL OUTLINE, R-PDSO-G24针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
风险等级:5.9其他特性:ESD PROTECTED
雪崩能效等级(Eas):96 mJ外壳连接:ISOLATED
配置:COMPLEX最小漏源击穿电压:60 V
最大漏极电流 (Abs) (ID):1.3 A最大漏极电流 (ID):1.25 A
最大漏源导通电阻:0.4 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):75 pFJEDEC-95代码:MS-013AD
JESD-30 代码:R-PDSO-G24元件数量:6
端子数量:24工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:N-CHANNEL
功耗环境最大值:1.39 W最大功率耗散 (Abs):1.4 W
最大脉冲漏极电流 (IDM):4 A认证状态:Not Qualified
子类别:FET General Purpose Power表面贴装:YES
端子形式:GULL WING端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICON最大关闭时间(toff):180 ns
最大开启时间(吨):125 nsBase Number Matches:1

TPIC1321LDW 数据手册

 浏览型号TPIC1321LDW的Datasheet PDF文件第2页浏览型号TPIC1321LDW的Datasheet PDF文件第3页浏览型号TPIC1321LDW的Datasheet PDF文件第4页浏览型号TPIC1321LDW的Datasheet PDF文件第5页浏览型号TPIC1321LDW的Datasheet PDF文件第6页浏览型号TPIC1321LDW的Datasheet PDF文件第7页 
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄꢇ  
ꢅ ꢈꢉꢊꢇ ꢋ ꢌꢉꢈꢍ ꢎꢂꢏ ꢐꢑ ꢌꢐ ꢊꢀ ꢑꢈꢁꢎ ꢒꢀ ꢑ ꢃꢀ ꢑꢏꢌ ꢇꢒ ꢐ ꢂ ꢃꢈ ꢇꢑ ꢓ ꢑꢇ  
ꢁꢒ ꢔ ꢑꢎꢌ ꢏꢕ ꢒ ꢖꢌꢊ ꢎꢎ ꢊꢗ  
SLIS042 − NOVEMBER 1994  
DW PACKAGE  
(TOP VIEW)  
Low r  
. . . 0.35 Typ  
Voltage Output . . . 60 V  
DS(on)  
OUTPUT1  
GATE4  
OUTPUT1  
GATE1  
Input Protection Circuitry . . . 18 V  
Pulsed Current . . . 4 A Per Channel  
Extended ESD Capability . . . 4000 V  
Direct Logic-Level Interface  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
2
SOURCE4  
SOURCE4  
GND  
DRAIN1  
DRAIN1  
DRAIN2  
DRAIN2  
OUTPUT2  
OUTPUT2  
GATE2  
3
4
5
GND  
6
description  
GATE5  
7
SOURCE6  
SOURCE6  
GATE6  
8
The TPIC1321L is a monolithic gate-protected  
logic-level power DMOS array that consists of six  
electrically isolated N-channel enhancement-  
mode DMOS transistors configured as 3-half  
H-bridges. Each transistor features integrated  
9
DRAIN3  
DRAIN3  
10  
11  
OUTPUT3  
OUTPUT3 12  
13 GATE3  
high-current zener diodes (Z  
and Z  
) to  
CXa  
CXb  
prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to  
4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-kΩ  
resistor.  
The TPIC1321L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for  
operation over the case temperature of 40°C to 125°C.  
schematic  
OUTPUT2  
17, 18  
GATE5 GATE2  
DRAIN2  
19, 20  
7
16  
21, 22  
23  
14, 15  
13  
DRAIN1  
GATE1  
DRAIN3  
GATE3  
Q1  
Q2  
Q3  
Z1  
Z2  
Z3  
Z
Z
C3b  
C1b  
Z
C2b  
D1  
D2  
Z
C3a  
Z
C1a  
Z
C2a  
11, 12  
D3  
OUTPUT3  
1, 24  
D4  
D5  
OUTPUT1  
Q4  
Q5  
Q6  
10  
2
Z4  
Z5  
Z6  
GATE6  
GATE4  
Z
C4b  
Z
C6b  
Z
C5b  
Z
C4a  
3, 4  
Z
C5a  
Z
C6a  
8, 9  
SOURCE6  
SOURCE4  
5, 6  
GND  
NOTE A: For correct operation, no terminal may be taken below GND.  
ꢀꢦ  
Copyright 1994, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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