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TPIC1310KTR PDF预览

TPIC1310KTR

更新时间: 2024-11-05 22:07:47
品牌 Logo 应用领域
德州仪器 - TI 晶体栅极晶体管功率场效应晶体管开关脉冲
页数 文件大小 规格书
11页 232K
描述
3-HALF H-BRIDGE GATE PROTECTED POWER DMOS ARRAY

TPIC1310KTR 技术参数

是否无铅:含铅生命周期:Obsolete
包装说明:PLASTIC, POWERFLEX-15针数:15
Reach Compliance Code:unknownECCN代码:EAR99
风险等级:5.84Is Samacsys:N
其他特性:ESD PROTECTED配置:COMPLEX
最小漏源击穿电压:30 V最大漏极电流 (Abs) (ID):3 A
最大漏极电流 (ID):3 A最大漏源导通电阻:0.37 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PSSO-G15
元件数量:6端子数量:15
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):13.9 W最大脉冲漏极电流 (IDM):12 A
认证状态:Not Qualified子类别:FET General Purpose Power
表面贴装:YES端子形式:GULL WING
端子位置:SINGLE晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

TPIC1310KTR 数据手册

 浏览型号TPIC1310KTR的Datasheet PDF文件第2页浏览型号TPIC1310KTR的Datasheet PDF文件第3页浏览型号TPIC1310KTR的Datasheet PDF文件第4页浏览型号TPIC1310KTR的Datasheet PDF文件第5页浏览型号TPIC1310KTR的Datasheet PDF文件第6页浏览型号TPIC1310KTR的Datasheet PDF文件第7页 
TPIC1310  
3-HALF H-BRIDGE GATE PROTECTED  
POWER DMOS ARRAY  
SLIS071 – DECEMBER 1997  
KTR or KTS PACKAGE  
(TOP VIEW)  
Configured for 3-Phase Brushless Motor  
Drive  
Low r  
. . . 0.25 Typ  
DS(on)  
1
V
DD  
High Voltage Output . . . 30 V  
2
OUTA  
UGA  
LGA  
3
Pulsed Current . . . 12 A Per Channel  
Input Transient and ESD Protection  
4
5
UGB  
Compatible With High-Side and Low-Side  
Current Sense Resistors  
6
SUB/GND  
SOURCE  
OUTB  
SOURCE  
SUB/GND  
LGB  
7
8
description  
9
10  
11  
12  
13  
14  
15  
The TPIC1310 is a monolithic gate-protected  
power DMOS array that consists of six electrically  
isolated N-channel enhancement-mode DMOS  
transistors configured as a three-half H-bridge.  
LGC  
UGC  
OUTC  
V
When suitably heat sunk, the TPIC1310 can drive  
motors requiring 2.5 A of phase current. The  
DMOS transistors are immune to second break-  
down effects and current crowding, problems  
often associated with bipolar transistors.  
DD  
Tab is SUB/GND  
The TPIC1310 is offered in 15-pin through-hole  
(KTS) and surface-mount (KTR) PowerFLEX  
packages and is characterized for operation over  
the case temperature range of 40°C to 125°C.  
schematic  
KTR PACKAGE  
KTS PACKAGE  
V
DD  
1, 15  
Q1  
Q2  
Q3  
14  
UGA  
LGA  
UGB  
UG  
C
3
5
13  
2
8
OUTB  
OUTC  
OUTA  
Q4  
Q5  
Q6  
LGB  
LGC  
13 k  
4
11  
13 k  
12  
13 k  
6, 10  
SUB/TAB/GND  
7, 9  
SOURCE  
NOTES: A. Terminals 1 and 15 must be externally connected.  
B. Terminals 6 and 10 must be connected to GND.  
C. Terminals 7 and 9 must be connected to the sense resistor or GND.  
D. No terminal may be taken greater than 0.5 V below GND.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerFLEX is a trademark of Texas Instruments Inc.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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TRANSISTOR | MOSFET | ARRAY | N-CHANNEL | 20V V(BR)DSS | 1.5A I(D) | SO