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TPIC1301DW PDF预览

TPIC1301DW

更新时间: 2024-11-06 02:58:35
品牌 Logo 应用领域
德州仪器 - TI 开关脉冲光电二极管晶体管
页数 文件大小 规格书
14页 269K
描述
3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY

TPIC1301DW 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SMALL OUTLINE, R-PDSO-G24针数:24
Reach Compliance Code:not_compliantECCN代码:EAR99
Factory Lead Time:1 week风险等级:5.86
其他特性:ESD PROTECTED雪崩能效等级(Eas):17.2 mJ
外壳连接:ISOLATED配置:COMPLEX
最小漏源击穿电压:60 V最大漏极电流 (Abs) (ID):2.3 A
最大漏极电流 (ID):2.25 A最大漏源导通电阻:0.275 Ω
FET 技术:METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss):75 pF
JEDEC-95代码:MS-013ADJESD-30 代码:R-PDSO-G24
元件数量:6端子数量:24
工作模式:ENHANCEMENT MODE最高工作温度:150 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
极性/信道类型:N-CHANNEL功耗环境最大值:1.39 W
最大功率耗散 (Abs):1.4 W最大脉冲漏极电流 (IDM):11.25 A
认证状态:Not Qualified子类别:FET General Purpose Power
表面贴装:YES端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
最大关闭时间(toff):65 ns最大开启时间(吨):80 ns

TPIC1301DW 数据手册

 浏览型号TPIC1301DW的Datasheet PDF文件第2页浏览型号TPIC1301DW的Datasheet PDF文件第3页浏览型号TPIC1301DW的Datasheet PDF文件第4页浏览型号TPIC1301DW的Datasheet PDF文件第5页浏览型号TPIC1301DW的Datasheet PDF文件第6页浏览型号TPIC1301DW的Datasheet PDF文件第7页 
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢄ  
ꢅ ꢇꢈꢉꢊ ꢋ ꢌꢈꢇꢍ ꢎꢂꢏ ꢐꢑ ꢌꢐ ꢉꢀ ꢑꢇꢁꢎ ꢒ ꢀꢑ ꢃꢀ ꢑꢏ  
ꢁꢒ ꢓ ꢑꢎꢌ ꢏꢔ ꢒꢕ ꢌꢉ ꢎꢎ ꢉꢖ  
SLIS037 − NOVEMBER 1994  
DW PACKAGE  
(TOP VIEW)  
Low r  
. . . 0.23 Typ  
High Voltage Output . . . 60 V  
DS(on)  
OUTPUT1  
GATE4  
OUTPUT1  
GATE1  
Extended ESD Capability . . . 4000 V  
Pulsed Current . . . 11.25 A Per Channel  
Fast Commutation Speed  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
2
SOURCE4  
SOURCE4  
GND  
DRAIN1  
DRAIN1  
DRAIN2  
DRAIN2  
OUTPUT2  
OUTPUT2  
GATE2  
3
4
5
description  
GND  
6
GATE5  
The TPIC1301 is a monolithic gate-protected  
power DMOS array that consists of six electrically  
isolated N-channel enhancement-mode DMOS  
transistors configured as three half H-bridges.  
Each transistor features integrated high-current  
7
SOURCE6  
SOURCE6  
GATE6  
8
9
DRAIN3  
DRAIN3  
10  
11  
OUTPUT3  
zener diodes (Z  
damage in the event that an overstress condition  
Z
) to prevent gate  
OUTPUT3 12  
13 GATE3  
CXa and CXb  
occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body  
model of a 100-pF capacitor in series with a 1.5-kresistor.  
The TPIC1301 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation  
over the case temperature range of 40°C to 125°C.  
schematic  
OUTPUT2  
17, 18  
GATE5  
GATE2 DRAIN2  
21, 22  
23  
7
16  
19, 20  
14, 15  
13  
DRAIN1  
GATE1  
DRAIN3  
GATE3  
Q1  
Q2  
Q3  
Z1  
Z2  
Z3  
Z
C1b  
Z
C2b  
Z
C3b  
D1  
D2  
D3  
Z
C1a  
Z
C2a  
Z
C3a  
1, 24  
11, 12  
OUTPUT3  
OUTPUT1  
D4  
D5  
Q4  
Q5  
Q6  
10  
2
Z4  
Z5  
Z6  
GATE6  
GATE4  
Z
C4b  
Z
C6b  
Z
C5b  
Z
C4a  
3, 4  
Z
C5a  
Z
C6a  
8, 9  
SOURCE6  
SOURCE4  
5, 6  
GND  
NOTE: For correct operation, no terminal pin may be taken below GND.  
ꢀꢥ  
Copyright 1994, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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