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ꢅ ꢇꢈꢉꢊ ꢋ ꢌꢈꢇꢍ ꢎꢂꢏ ꢐꢑ ꢌꢐ ꢉꢀ ꢑꢇꢁꢎ ꢒ ꢀꢑ ꢃꢀ ꢑꢏ
ꢁꢒ ꢓ ꢑꢎꢌ ꢏꢔ ꢒꢕ ꢌꢉ ꢎꢎ ꢉꢖ
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SLIS037 − NOVEMBER 1994
DW PACKAGE
(TOP VIEW)
• Low r
. . . 0.23 Ω Typ
• High Voltage Output . . . 60 V
DS(on)
OUTPUT1
GATE4
OUTPUT1
GATE1
• Extended ESD Capability . . . 4000 V
• Pulsed Current . . . 11.25 A Per Channel
• Fast Commutation Speed
1
24
23
22
21
20
19
18
17
16
15
14
2
SOURCE4
SOURCE4
GND
DRAIN1
DRAIN1
DRAIN2
DRAIN2
OUTPUT2
OUTPUT2
GATE2
3
4
5
description
GND
6
GATE5
The TPIC1301 is a monolithic gate-protected
power DMOS array that consists of six electrically
isolated N-channel enhancement-mode DMOS
transistors configured as three half H-bridges.
Each transistor features integrated high-current
7
SOURCE6
SOURCE6
GATE6
8
9
DRAIN3
DRAIN3
10
11
OUTPUT3
zener diodes (Z
damage in the event that an overstress condition
Z
) to prevent gate
OUTPUT3 12
13 GATE3
CXa and CXb
occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body
model of a 100-pF capacitor in series with a 1.5-kΩ resistor.
The TPIC1301 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of −40°C to 125°C.
schematic
OUTPUT2
17, 18
GATE5
GATE2 DRAIN2
21, 22
23
7
16
19, 20
14, 15
13
DRAIN1
GATE1
DRAIN3
GATE3
Q1
Q2
Q3
Z1
Z2
Z3
Z
C1b
Z
C2b
Z
C3b
D1
D2
D3
Z
C1a
Z
C2a
Z
C3a
1, 24
11, 12
OUTPUT3
OUTPUT1
D4
D5
Q4
Q5
Q6
10
2
Z4
Z5
Z6
GATE6
GATE4
Z
C4b
Z
C6b
Z
C5b
Z
C4a
3, 4
Z
C5a
Z
C6a
8, 9
SOURCE6
SOURCE4
5, 6
GND
NOTE: For correct operation, no terminal pin may be taken below GND.
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Copyright 1994, Texas Instruments Incorporated
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2−1
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