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TPA5052RSAR PDF预览

TPA5052RSAR

更新时间: 2024-10-26 03:58:47
品牌 Logo 应用领域
德州仪器 - TI 消费电路商用集成电路
页数 文件大小 规格书
10页 262K
描述
STEREO DIGITAL AUDIO LIP-SYNC DELAY

TPA5052RSAR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC16,.16SQ,20针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01Factory Lead Time:1 week
风险等级:0.77商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PQCC-N16JESD-609代码:e4
长度:4 mm湿度敏感等级:2
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC16,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Other Consumer ICs
最大压摆率:3 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4 mmBase Number Matches:1

TPA5052RSAR 数据手册

 浏览型号TPA5052RSAR的Datasheet PDF文件第2页浏览型号TPA5052RSAR的Datasheet PDF文件第3页浏览型号TPA5052RSAR的Datasheet PDF文件第4页浏览型号TPA5052RSAR的Datasheet PDF文件第5页浏览型号TPA5052RSAR的Datasheet PDF文件第6页浏览型号TPA5052RSAR的Datasheet PDF文件第7页 
A5052  
TP  
TPA5052  
www.ti.com  
SLOS500AJUNE 2006REVISED AUGUST 2006  
STEREO DIGITAL AUDIO LIP-SYNC DELAY  
FEATURES  
APPLICATIONS  
Digital Audio Format: 16-24-bit I2S  
Single Serial Input Port  
High Definition TV Lip-Sync Delay  
Flat Panel TV Lip-Sync Delay  
Home Theater Rear-Channel Effects  
Wireless Speaker Front-Channel  
Synchronization  
Delay Time: 170 ms/ch at fs = 48 kHz  
Delay Resolution: 256 samples  
Delay Memory Cleared on Power-Up or After  
Delay Changes  
Camcorders  
– Eliminates Erroneous Data From Being  
Output  
DESCRIPTION  
The TPA5052 accepts a single serial audio input,  
buffers the data for a selectable period of time, and  
outputs the delayed audio data on a single serial  
output. In systems with complex video processing  
algorithms, one device allows delay of up to  
170 ms/ch (fs = 48 kHz) to synchronize the audio  
stream to the video stream. If more delay is needed,  
the devices can be connected in series.  
3.3 V Operation With 5 V Tolerant I/O  
Supports Audio Bit Clock Rates of 32 to 64 fs  
with fs = 32 kHz–192 kHz  
No External Crystal or Oscillator Required  
– All Internal Clocks Generated From the  
Audio Clock  
Surface Mount 4mm × 4mm, 16-pin QFN  
Package  
SIMPLIFIED APPLICATION DIAGRAM  
Audio Processor  
Digital Amplifier  
SCLK  
TAS5504A  
+TAS5122  
TAS3103A  
or  
3.3 V  
TPA5052  
ATSC  
Processor  
SCLK  
BCLK  
LRCLK  
DATA  
BCLK  
BCLK  
LRCLK  
DATA  
LRCLK  
DATA  
DATA_OUT  
5
Fixed Delay  
Control  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006, Texas Instruments Incorporated  

TPA5052RSAR 替代型号

型号 品牌 替代类型 描述 数据表
TPA5052RSATG4 TI

完全替代

STEREO DIGITAL AUDIO LIP-SYNC DELAY
TPA5052RSAT TI

完全替代

STEREO DIGITAL AUDIO LIP-SYNC DELAY
TPA5052RSARG4 TI

类似代替

STEREO DIGITAL AUDIO LIP-SYNC DELAY

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