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TP3067J PDF预览

TP3067J

更新时间: 2024-11-04 22:42:03
品牌 Logo 应用领域
美国国家半导体 - NSC 解码器编解码器电信集成电路PC
页数 文件大小 规格书
18页 277K
描述
``Enhanced' Serial Interface CMOS CODEC/Filter COMBO

TP3067J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.8
压伸定律:A-LAW滤波器:YES
最大增益公差:0.15 dBJESD-30 代码:R-GDIP-T20
JESD-609代码:e0长度:24.51 mm
线性编码:NOT AVAILABLE负电源额定电压:-5 V
功能数量:1端子数量:20
工作模式:SYNCHRONOUS/ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:+-5 V
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Codecs最大压摆率:10 mA
标称供电电压:5 V表面贴装:NO
技术:CMOS电信集成电路类型:PCM CODEC
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm

TP3067J 数据手册

 浏览型号TP3067J的Datasheet PDF文件第2页浏览型号TP3067J的Datasheet PDF文件第3页浏览型号TP3067J的Datasheet PDF文件第4页浏览型号TP3067J的Datasheet PDF文件第5页浏览型号TP3067J的Datasheet PDF文件第6页浏览型号TP3067J的Datasheet PDF文件第7页 
October 1991  
TP3064, TP3067  
‘‘Enhanced’’ Serial Interface  
CMOS CODEC/Filter COMBO  
General Description  
The TP3064 (m-law) and TP3067 (A-law) are monolithic  
PCM CODEC/Filters utilizing the A/D and D/A conversion  
architecture shown in Figure 1, and a serial PCM interface.  
The devices are fabricated using National’s advanced dou-  
ble-poly CMOS process (microCMOS).  
É
Features  
Y
Complete CODEC and filtering system including:  
Ð Transmit high-pass and low-pass filtering  
Ð Receive low-pass filter with sin x/x correction  
Ð Active RC noise filters  
Ð m-law or A-law compatible COder and DECoder  
Ð Internal precision voltage reference  
Ð Serial I/O interface  
Ð Internal auto-zero circuitry  
Ð Receive push-pull power amplifiers  
m-lawÐTP3064  
Similar to the TP305X family, these devices feature an addi-  
tional Receive Power Amplifier to provide push-pull bal-  
anced output drive capability. The receive gain can be ad-  
justed by means of two external resistors for an output level  
Y
Y
Y
Y
Y
Y
Y
Y
Y
g
of up to 6.6V across a balanced 600X load.  
A-lawÐTP3067  
Also included is an Analog Loopback switch and a TS out-  
X
put.  
Designed for D3/D4 and CCITT applications  
g
5V operation  
See also AN-370, ‘‘Techniques for Designing with CODEC/  
Filter COMBO Circuits.’’  
Low operating powerÐtypically 70 mW  
Power-down standby modeÐtypically 3 mW  
Automatic power-down  
TTL or CMOS compatible digital interfaces  
Maximizes line interface card circuit density  
COMBOÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corpora-  
tion.  
Block Diagram  
TL/H/5070–1  
FIGURE 1  
C
1995 National Semiconductor Corporation  
TL/H/5070  
RRD-B30M115/Printed in U. S. A.  

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