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TP3052J-C PDF预览

TP3052J-C

更新时间: 2024-01-17 02:32:00
品牌 Logo 应用领域
美国国家半导体 - NSC 解码器编解码器
页数 文件大小 规格书
16页 668K
描述
IC,PCM CODEC,SINGLE,CMOS,DIP,18PIN,CERAMIC

TP3052J-C 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP, SOP18,.4Reach Compliance Code:unknown
风险等级:5.85压伸定律:MU-LAW
滤波器:YES最大增益公差:0.15 dB
JESD-30 代码:R-PDSO-G18JESD-609代码:e0
线性编码:NOT AVAILABLE负电源额定电压:-5 V
功能数量:1端子数量:18
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP18,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:+-5 V
认证状态:Not Qualified子类别:Codecs
最大压摆率:9 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:PCM CODEC温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

TP3052J-C 数据手册

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March 2005  
TP3054-X, TP3057-X  
Extended Temperature Serial Interface CODEC/Filter  
COMBO® Family  
General Description  
Features  
n −40˚C to +85˚C operation  
The TP3054, TP3057 family consists of µ-law and A-law  
monolithic PCM CODEC/filters utilizing the A/D and D/A  
conversion architecture shown in Figure 1, and a serial PCM  
interface. The devices are fabricated using National’s ad-  
vanced double-poly CMOS process (microCMOS).  
n Complete CODEC and filtering system (COMBO)  
including:  
— Transmit high-pass and low-pass filtering  
— Receive low-pass filter with sin x/x correction  
— Active RC noise filters  
The encode portion of each device consists of an input gain  
adjust amplifier, an active RC pre-filter which eliminates very  
high frequency noise prior to entering a switched-capacitor  
band-pass filter that rejects signals below 200 Hz and above  
3400 Hz. Also included are auto-zero circuitry and a com-  
panding coder which samples the filtered signal and en-  
codes it in the companded µ-law or A-law PCM format. The  
decode portion of each device consists of an expanding  
decoder, which reconstructs the analog signal from the com-  
panded µ-law or A-law code, a low-pass filter which corrects  
for the sin x/x response of the decoder output and rejects  
signals above 3400 Hz followed by a single-ended power  
amplifier capable of driving low impedance loads. The de-  
vices require two 1.536 MHz, 1.544 MHz or 2.048 MHz  
transmit and receive master clocks, which may be asynchro-  
nous; transmit and receive bit clocks, which may vary from  
64 kHz to 2.048 MHz; and transmit and receive frame sync  
pulses. The timing of the frame sync pulses and PCM data is  
compatible with both industry standard formats.  
— µ-law or A-law compatible COder and DECoder  
— Internal precision voltage reference  
— Serial I/O interface  
— Internal auto-zero circuitry  
n µ-law, 16-pinTP3054  
n A-law, 16-pinTP3057  
n Designed for D3/D4 and CCITT applications  
n
5V operation  
n Low operating powertypically 50 mW  
n Power-down standby modetypically 3 mW  
n Automatic power-down  
n TTL or CMOS compatible digital interfaces  
n Maximizes line interface card circuit density  
n Dual-In-Line or PCC surface mount packages  
n See also AN-370, “Techniques for Designing with  
CODEC/Filter COMBO Circuits”  
Connection Diagrams  
Dual-In-Line Package  
Plastic Chip Carriers  
00867401  
Top View  
Order Number TP3054N-X  
NS Package Number N16E  
Order Number TP3054WM-X  
NS Package Number M16B  
00867408  
Top View  
Order Number TP3057V-X  
NS Package Number V20A  
COMBO® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.  
© 2005 National Semiconductor Corporation  
DS008674  
www.national.com  

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