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TP2535N3-GP014 PDF预览

TP2535N3-GP014

更新时间: 2024-11-19 15:54:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
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5页 597K
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TP2535N3-GP014 数据手册

 浏览型号TP2535N3-GP014的Datasheet PDF文件第2页浏览型号TP2535N3-GP014的Datasheet PDF文件第3页浏览型号TP2535N3-GP014的Datasheet PDF文件第4页浏览型号TP2535N3-GP014的Datasheet PDF文件第5页 
Supertex inc.  
TP2535  
P-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
Low threshold (-2.4V max.)  
High input impedance  
Low input capacitance (60pF typical)  
Fast switching speeds  
Low on-resistance  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structure and Supertex’s  
well-proven, silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and the high input impedance  
and positive temperature coefficient inherent in MOS devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced secondary  
breakdown.  
Free from secondary breakdown  
Low input and output leakage  
Applications  
Logic level interfaces - ideal for TTL and CMOS  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
Solid state relays  
Battery operated systems  
Photo voltaic drives  
Analog switches  
General purpose line drivers  
Telecom switches  
Ordering Information  
Product Summary  
RDS(ON)  
ID(ON)  
Part Number  
Package Option  
Packing  
VGS(th)  
(max)  
BVDSS/BVDGS  
(max)  
(min)  
TP2535N3-G  
3-Lead TO-92  
1000/Bag  
-350V  
25Ω  
-2.4A  
-0.4V  
TP2535N3-G P002  
TP2535N3-G P003  
Pin Configuration  
TP2535N3-G P005 3-Lead TO-92  
TP2535N3-G P013  
2000/Reel  
DRAIN  
TP2535N3-G P014  
SOURCE  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
GATE  
TO-92  
Absolute Maximum Ratings  
Parameter  
Product Marking  
Value  
BVDSS  
BVDGS  
±20V  
Drain-to-source voltage  
Drain-to-gate voltage  
SiTP  
2 5 3 5  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
= “Green” Packaging  
Gate-to-source voltage  
Operating and storage temperature  
-55OC to +150OC  
Package may or may not include the following marks: Si or  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
TO-92  
Typical Thermal Resistance  
Package  
θja  
TO-92  
132OC/W  
Doc.# DSFP-TP2535  
B081613  
Supertex inc.  
www.supertex.com  

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